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P87LPC779 cmos single-chip 8-bit 80c51 microcontroller with 128-byte data ram, 8 kb otp rev. 02 03 may 2004 product data 1. general description the P87LPC779 is a 20-pin single-chip microcontroller designed for low pin count applications demanding high-integration, low cost solutions over a wide range of performance requirements. a member of the philips low pin count family, the P87LPC779 offers a four channel, 8-bit a/d converter, two dac outputs, programmable oscillator con?gurations for high and low speed crystals or rc operation, wide operating voltage range, programmable port output con?gurations, selectable schmitt trigger inputs, led drive outputs, and a built-in watchdog timer. the P87LPC779 is based on an accelerated 80c51 processor architecture that executes instructions at twice the rate of standard 80c51 devices. 2. features n an accelerated 80c51 cpu provides instruction cycle times of 300 ns to 600 ns for all instructions except multiply and divide when executing at 20 mhz. n 2.7 v to 5.5 v operating range for digital functions. n two 8-bit digital to analog converters. n four channel, 8-bit analog to digital converter. conversion time is 9.3 m s with a 20 mhz crystal. n i 2 c-bus communication port and full duplex uart. n internal oscillator 2.5 %. the internal oscillator option allows operation with no external oscillator components. n two analog comparators. n eight keypad interrupt inputs, plus two additional external interrupt inputs. n watchdog timer with separate on-chip oscillator, requiring no external components. the watchdog time-out time is selectable from eight values. n 20-pin tssop package.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 2 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 3. ordering information table 1: ordering information type number package name description temperature range version P87LPC779fdh tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm - 40 c to +85 c sot360-1
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 3 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 4. block diagram fig 1. block diagram. accelerated 80c51 cpu 8 kb code eprom 128-byte data ram port 1 configurable i/os port 0 configurable i/os keypad interrupt programmable oscillator divider cpu clock configurable oscillator on-chip rc oscillator internal bus crystal or resonator power monitor (power-on reset, brownout reset) 002aaa815 uart i 2 c timer 0, 1 watchdog timer and oscillator dac output analog comparators a/d converter port 2 configurable i/os
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 4 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. (1) the P87LPC779 does not support access to external data memory. however, the user con?guration bytes are accessed via the movx instruction as if they were in external data memory. fig 2. memory map. unused code memory space unused code memory space 32-byte customer code space (accessible via movc) 8 kbytes on-chip data memory 128 bytes on-chip data memory (directly and indirectly addressable via movc) special function registers (only directly addressable) configuration bytes ucfg1, ucfg2 (accessible via movx) unused space interrupt vectors on-chip code memory space 0000h unused space 16 bytes bit-addressable 00h 0000h fd00h fd01h ffffh 7fh ffh 80h on-chip data memory space external data memory space (1) 1fffh 2000h fce0h fcffh ffffh 002aaa816
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 5 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5. pinning information 5.1 pinning 5.2 pin description fig 3. 20 pin dip and so con?guration. handbook, halfpage P87LPC779 002aaa814 1 2 3 4 5 6 7 8 9 10 cmp2/p0.0 dac0/p1.7 dac1/p1.6 rst/p1.5 v ss x1/p2.1 x2/clkout/p2.0 int1/p1.4 sda/int0/p1.3 scl/t0/p1.2 p0.1/cin2b p0.2/cin2a p0.3/cin1b/ad0 p0.4/cin1a/ad1 p0.5/cmpref/ad2 v dd p0.6/cmp1/ad3 p0.7/t1 p1.0/txd p1.1/rxd 20 19 18 17 16 15 14 13 12 11 table 2: pin description symbol pin type description p0.0 - p0.7 1, 20-16, 14, 13 i/o port 0: port 0 is an 8-bit i/o port with a user-con?gurable output type. port 0 latches are con?gured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the prhi bit in the ucfg1 con?guration byte. the operation of port 0 pins as inputs and outputs depends upon the port con?guration selected. each port pin is con?gured independently. refer to section 8.9 i/o ports and table 55 dc electrical characteristics for details. the keypad interrupt feature operates with port 0 pins. port 0 also provides various special functions as described below: p0.0 1 o cmp2 comparator 2 output. p0.1 20 i cin2b comparator 2 positive input b. p0.2 19 i cin2a comparator 2 positive input a. p0.3 18 i cin1b comparator 1 positive input b. i ad0 a/d channel 0 input. p0.4 17 i cin1a comparator 1 positive input a. i ad1 a/d channel 1 input. p0.5 16 i cmpref comparator reference (negative) input. i ad2 a/d channel 2 input. p0.6 14 o cmp1 comparator 1 output. i ad3 a/d channel 3 input. p0.7 13 i/o t1 timer/counter 1 external count input or over?ow output.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 6 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. p1.0 - p1.7 12-8, 4, 3, 2 i/o port 1: port 1 is an 8-bit i/o port with a user-con?gurable output type, except for three pins as noted below. port 1 latches are con?gured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the prhi bit in the ucfg1 configuration byte. the operation of the configurable port 1 pins as inputs and outputs depends upon the port con?guration selected. each of the con?gurable port pins are programmed independently. refer to section 8.9 i/o ports and table 55 dc electrical characteristics for details. port 1 also provides various special functions as described below: p1.0 12 o txd transmitter output for the serial port. p1.1 11 i rxd receiver input for the serial port. p1.2 10 i/o t0 timer/counter 0 external count input or over?ow output. i/o scl i 2 c-bus serial clock input/output. when con?gured as an output, p1.2 is open drain, in order to conform to i 2 c-bus speci?cations. p1.3 9 i int0 external interrupt 0 input. i/o sda i 2 c-bus serial data input/output. when con?gured as an output, p1.3 is open drain, in order to conform to i 2 c-bus speci?cations. p1.4 8 i int1 external interrupt 1 input. p1.5 4 i rst external reset input (if selected via eprom con?guration). a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor begins execution at address 0. when used as a port pin, p1.5 is a schmitt trigger input only. p1.6 3 o dac1 output from digital to analog converter 1. p1.7 2 o dac0 output from digital to analog converter 0. p2.0 - p2.1 7, 6 i/o port 2: port 2 is a 2-bit i/o port with a user-con?gurable output type. port 2 latches are con?gured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the prhi bit in the ucfg1 con?guration byte. the operation of port 2 pins as inputs and outputs depends upon the port con?guration selected. each port pin is con?gured independently. refer to section 8.9 i/o ports and table 55 dc electrical characteristics for details. port 2 also provides various special functions as described below: p2.0 7 o x2 output from the oscillator ampli?er (when a crystal oscillator option is selected via the eprom con?guration. o clkout cpu clock divided by 6 clock output when enabled via sfr bit and in conjunction with internal rc oscillator or external clock input. p2.1 6 i x1 input to the oscillator circuit and internal clock generator circuits (when selected via the eprom con?guration). v ss 5i ground: 0 v reference. v dd 15 i power supply: this is the power supply voltage for normal operation as well as idle and power-down modes. table 2: pin description continued symbol pin type description
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 7 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. logic symbol fig 4. logic symbol. v dd v ss P87LPC779 port 0 port 2 port 1 txd dac0 dac1 rxd t0 int0 int1 rst scl sda 002aaa856 cmp2 cin2b cin2a cin1b cin1a cmpref cmp1 t1 clkout/x2 x1 ad0 ad1 ad2 ad3
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 8 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. special function registers remark: special function registers (sfrs) accesses are restricted in the following ways: ? user must not attempt to access any sfr locations not de?ned. ? accesses to any de?ned sfr locations must be strictly for the functions for the sfrs. ? sfr bits labeled -, 0 or 1 can only be written and read as follows: C - unless otherwise speci?ed, must be written with 0, but can return any value when read (even if it was written with 0). it is a reserved bit and may be used in future derivatives. C 0 must be written with 0, and will return a 0 when read. C 1 must be written with 1, and will return a 1 when read.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 02 03 may 2004 9 of 74 table 3: special function registers * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex bit address e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h 00h bit address c7 c6 c5 c4 c3 c2 c1 c0 adcon* a/d control c0h enadc adci adcs rcclk aadr1 aadr0 02h auxr1 auxiliary function register a2h kbf bod boi lpep srst 0 - dps 02h bit address f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h 00h cmp1 comparator 1 control register ach - - ce1 cp1 cn1 oe1 co1 cmf1 00h cmp2 comparator 2 control register adh - - ce2 cp2 cn2 oe2 co2 cmf2 00h dac0 a/d result / read dac0 output value / write c5h 00h dac1 dac1 output value c6h 00h divm cpu clock divide-by-m control 95h 00h dptr data pointer (2 bytes) dph data pointer high 83h 00h dpl data pointer low 82h 00h bit address cf ce cd cc cb ca c9 c8 i2cfg* i 2 c-bus con?guration register c8h/rd slaven mastrq 0 tirun - - ct1 ct0 00h c8h/wr slaven mastrq clrti tirun - - ct1 ct0 bit address df de dd dc db da d9 d8 i2con* i 2 c-bus control register d8h/rd rdat atn drdy arl str stp master - 80h d8h/wr cxa idle cdr carl cstr cstp xstr xstp i2dat i 2 c-bus data register d9h/rd rdat 0 00000080h d9h/wr xdat xxxxxxx bit address af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ewd ebo es et1 ex1 et0 ex0 00h bit address ef ee ed ec eb ea e9 e8 ien1* interrupt enable 1 e8h eti - ec1 ead - ec2 ekb ei2 00h
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 02 03 may 2004 10 of 74 bit address bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h - pwd pbo ps pt1 px1 pt0 px0 00h ip0h interrupt priority 0 high b7h - pwdh pboh psh pt1h px1h pt0h px0h 00h bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h pti - pc1 pad - pc2 pkb pi2 00h ip1h interrupt priority 1 high f7h ptih - pc1h padh - pc2h pkbh pi2h 00h kbi keyboard interrupt 86h 00h bit address 87 86 85 84 83 82 81 80 p0* port 0 80h t1 cmp1 cmpref cin1a cin1b cin2a cin2b cmp2 [1] bit address 97 96 95 94 93 92 91 90 p1* port 1 90h dac0 dac1 rst int1 int0 t0 rxd txd [1] bit address a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h - - - - - - x1 x2 [1] p0m1 port 0 output mode 1 84h (p0m1.7) (p0m1.6) (p0m1.5) (p0m1.4) (p0m1.3) (p0m1.2) (p0m1.1) (p0m1.0) 00h p0m2 port 0 output mode 2 85h (p0m2.7) (p0m2.6) (p0m2.5) (p0m2.4) (p0m2.3) (p0m2.2) (p0m2.1) (p0m2.0) 00h p1m1 port 1 output mode 1 91h (p1m1.7) (p1m1.6) - (p1m1.4) - - (p1m1.1) (p1m1.0) 00h p1m2 port 1 output mode 2 92h (p1m2.7) (p1m2.6) - (p1m2.4) - - (p1m2.1) (p1m2.0) 00h p2m1 port 2 output mode 1 a4h p2s p1s p0s enclk ent1 ent0 (p2m1.1) (p2m1.0) 00h p2m2 port 2 output mode 2 a5h - - - - - - (p2m2.1) (p2m2.0) 00h pcon power control register 87h smod1 smod0 bof pof gf1 gf0 pd idl [2] bit address d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00h pt0ad port 0 digital input disable f6h 00h bit address 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h sbuf serial port data buffer register 99h xxh saddr serial port address register a9h 00h saden serial port address enable b9h 00h table 3: special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 02 03 may 2004 11 of 74 [1] i/o port values at reset are determined by the prhi bit in the ucfg1 con?guration byte. [2] the pcon reset value is xxbof pof - 0000b. the bof and pof ?ags are not affected by reset. the pof ?ag is set by hardware up on power up. the bof ?ag is set by the occurrence of a brownout reset/interrupt and upon power up. [3] the wdcon reset value is xx11 0000b for a watchdog reset, xx01 0000b for all other reset causes if the watchdog is enabled, and xx00 0000b for all other reset causes if the watchdog is disabled. sp stack pointer 81h 07h bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h th0 timer0 high 8ch 00h th1 timer1 high 8dh 00h tl0 timer0 low 8ah 00h tl1 timer1 low 8bh 00h tmod timer0 and 1 mode 89h gate c/t m1 m0 gate c/t m1 m0 00h wdcon watchdog control register a7h - - wdovf wdrun wdclk wds2 wds1 wds0 [3] wdrst watchdog reset register a6h xxh table 3: special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 12 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8. functional description remark: please refer to the P87LPC779 users manual for a more detailed functional description. 8.1 enhanced cpu the P87LPC779 uses an enhanced 80c51 cpu which runs at twice the speed of standard 80c51 devices. this means that the performance of the P87LPC779 running at 5 mhz is exactly the same as that of a standard 80c51 running at 10 mhz. a machine cycle consists of 6 oscillator cycles, and most instructions execute in 6 or 12 clocks. a user con?gurable option allows restoring standard 80c51 execution timing. in that case, a machine cycle becomes 12 oscillator cycles. in the following sections, the term cpu clock is used to refer to the clock that controls internal instruction execution. this may sometimes be different from the externally applied clock, as in the case where the part is con?gured for standard 80c51 timing by means of the clkr con?guration bit or in the case where the clock is divided down via the setting of the divm register. these features are described in the section 8.10 oscillator on page 34 . 8.2 analog functions the P87LPC779 incorporates analog peripheral functions: an adc, two analog comparators, and two dacs. in order to give the best analog function performance and to minimize power consumption, pins that are actually being used for analog functions must have the digital outputs (except for the dac output pins) and the digital inputs must also be disabled. digital outputs are disabled by putting the port output into the input only (high impedance) mode as described in the section 8.9 i/o ports on page 29 . digital inputs on port 0 may be disabled through the use of the pt0ad register. each bit in this register corresponds to one pin of port 0. setting the corresponding bit in pt0ad disables that pins digital input. port bits that have their digital inputs disabled will be read as 0 by any instruction that accesses the port. 8.3 analog to digital converter the P87LPC779 incorporates a four channel, 8-bit a/d converter. the a/d inputs are alternate functions on four port 0 pins. because the device has a very limited number of pins, the a/d power supply and references are shared with the processor power pins, v dd and v ss . the a/d converter operates down to a v dd supply of 3.0 v. the a/d converter circuitry consists of a 4-input analog multiplexer and an 8-bit successive approximation adc. the a/d employs a ratiometric potentiometer which guarantees dac monotonicity. the a/d converter is controlled by the special function register adcon. details of adcon are shown in tables 4 and 5 . the a/d must be enabled by setting the enadc bit at least 10 microseconds before a conversion is started, to allow time for
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 13 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. the a/d to stabilize. prior to the beginning of an a/d conversion, one analog input pin must be selected for conversion via the aadr1 and aadr0 bits. these bits cannot be changed while the a/d is performing a conversion. an a/d conversion is started by setting the adcs bit, which remains set while the conversion is in progress. when the conversion is complete, the adcs bit is cleared and the adci bit is set. when adci is set, it will generate an interrupt if the interrupt system is enabled, the a/d interrupt is enabled (via the ead bit in the ie1 register), and the a/d interrupt is the highest priority pending interrupt. when a conversion is complete, the result is contained in the register dac0 and can be read to get the adc result. this value will not change until another conversion is started. before another a/d conversion may be started, the adci bit must be cleared by software. the a/d channel selection may be changed by the same instruction that sets adcs to start a new conversion, but not by the same instruction that clears adci. the connections of the a/d converter are shown in figure 5 . the ideal a/d result may be calculated as follows: (1) table 4: adcon - a/d control register (address c0h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol enadc dac1 dac0 adci adcs rcclk aadr1 aadr0 table 5: adcon - a/d control register (address c0h) bit description bit symbol description 7 enadc when enadc = 1, the a/d is enabled and conversions may take place. must be set 10 microseconds before a conversion is started. enadc cannot be cleared while adcs or adci are 1. 6 dac1 when endac1 = 1, dac1 is enabled to provide an analog output voltage. refer to section 8.5 digital to analog converter (dac) outputs on page 17 . 5 dac0 when endac1 = 0, dac0 is enabled to provide an analog output voltage. writable while adcs and adci are 0. refer to section 8.5 digital to analog converter (dac) outputs on page 17 for more detail. enadc and endac0 should not be set at the same time. result v in v ss C () 256 v dd v ss C -------------------------- round result to the nearest integer () =
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 14 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.4 a/d timing the a/d may be clocked in one of two ways. the default is to use the cpu clock as the a/d clock source. when used in this manner, the a/d completes a conversion in 31 machine cycles. the a/d may be operated up to the maximum cpu clock rate of 20 mhz, giving a conversion time of 9.3 m s. the formula for calculating a/d conversion time when the cpu clock runs the a/d is: 186 m s / cpu clock rate (in mhz). to obtain accurate a/d conversion results, the cpu clock must be at least 1 mhz. the a/d may also be clocked by the on-chip rc oscillator, even if the rc oscillator is not used as the cpu clock. this is accomplished by setting the rcclk bit in adcon. this arrangement has several advantages. first, the a/d conversion time is faster at lower cpu clock rates. also, the cpu may be run at speeds below 1 mhz without affecting a/d accuracy. finally, the power-down mode may be used to completely shut down the cpu and its oscillator, along with other peripheral functions, in order to obtain the best possible a/d accuracy. 4 adci a/d conversion complete/interrupt ?ag. this ?ag is set when an a/d conversion is completed. this bit will cause a hardware interrupt if enabled and of suf?cient priority. must be cleared by software. 3 adcs a/d start. setting this bit by software starts the conversion of the selected a/d input. adcs remains set while the a/d conversion is in progress and is cleared automatically upon completion. while adcs or adci are one, new start commands are ignored. see ta b l e 6 . 2 rcclk when rcclk = 0, the cpu clock is used as the a/d clock. when rcclk = 1, the internal rc oscillator is used as the a/d clock. this bit is writable while adcs and adci are 0. 1, 0 aadr1, 0 along with aadr0, selects the a/d channel to be converted. these bits can only be written while adcs and adci are 0. see ta b l e 7 . table 6: adcon - adci, adcs a/d status adci, adcs a/d status 0 0 a/d not busy, a conversion can be started 0 1 a/d busy, the start of a new conversion is blocked. 1 0 an a/d conversion is complete. adci must be cleared prior to starting a new conversion. 1 1 an a/d conversion is complete. adci must be cleared prior to starting a new conversion. this state exists for one machine cycle as an a/d conversion is completed. table 7: adcon - aadr1, aadr0 a/d input selection aadr1, aadr0 a/d input selected 0 0 ad0 (p0.3) 0 1 ad1 (p0.4) table 5: adcon - a/d control register (address c0h) bit description continued bit symbol description
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 15 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. when the a/d is operated from the rcclk while the cpu is running from another clock source, 3 or 4 machine cycles are used to synchronize a/d operation. the time can range from a minimum of 3 machine cycles (at the cpu clock rate) + 108 rc clocks to a maximum of 4 machine cycles (at the cpu clock rate) + 112 rc clocks. example a/d conversion times at various cpu clock rates are shown in ta b l e 8 . in the table, maximum times for rcclk = 1 use an rc clock frequency of 6 mhz. minimum times for rcclk = 1 use an rc clock frequency of. nominal time assume an ideal rc clock frequency of 6 mhz and an average of 3.5 machine cycles at the cpu clock rate. 8.4.1 the a/d in power-down and idle modes while using the cpu clock as the a/d clock source, the idle mode may be used to conserve power and/or to minimize system noise during the conversion. cpu operation will resume and idle mode terminate automatically when a conversion is complete if the a/d interrupt is active. in idle mode, noise from the cpu itself is eliminated, but noise from the oscillator and any other on-chip peripherals that are running will remain. the cpu may be put into power-down mode when the a/d is clocked by the on-chip rc oscillator (rcclk = 1). this mode gives the best possible a/d accuracy by eliminating most on-chip noise sources. if the power-down mode is entered while the a/d is running from the cpu clock (rcclk = 0), the a/d will abort operation and will not wake up the cpu. the contents of dac0 will be invalid when operation does resume. table 8: example a/d conversion times cpu clock rate rcclk = 0 rcclk = 1 minimum nominal maximum 32 khz na 563.4 m s 659 m s 757 m s 1 mhz 186 m s 32.4 m s 39.3 m s 48.9 m s 4 mhz 46.5 m s 18.9 m s 23.6 m s 30.1 m s 11.0592 mhz 16.8 m s16 m s 20.2 m s 27.1 m s 12 mhz 15.5 m s 15.9 m s 20.1 m s 26.9 m s 16 mhz 11.6 m s 15.5 m s 19.7 m s 26.4 m s 20 mhz 9.3 m s 15.3 m s 19.4 m s 26.1 m s fig 5. a/d converter connections. 002aaa616 ad0 (p0.3) 00 ad1 (p0.4) a/d converter 01 ad2 (p0.5) 10 ad3 (p0.6) 11 adcon adcon dac0 adcon dac0 (a/d result, read dac0) v ref + = v dd v ref - = v ss
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 16 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. when an a/d conversion is started, power-down or idle mode must be activated within two machine cycles in order to have the most accurate a/d result. these two machine cycles are counted at the cpu clock rate. when using the a/d with either power-down or idle mode, care must be taken to insure that the cpu is not restarted by another interrupt until the a/d conversion is complete. the possible causes of wake-up are different in power-down and idle modes. a/d accuracy is also affected by noise generated elsewhere in the application, power supply noise, and power supply regulation. since the P87LPC779 power pins are also used as the a/d reference and supply, the power supply has a very direct affect on the accuracy of a/d readings. using the a/d without power-down mode while the clock is divided through the use of clkr or divm has an adverse effect on a/d accuracy. 8.4.2 code examples for the a/d the ?rst piece of sample code shows an example of port con?guration for use with the a/d. this example sets up the pins so that all four a/d channels may be used. port con?guration for analog functions is described in section 8.2 analog functions on page 12 . ; set up port pins for a/d conversion, without affecting other pins. mov pt0ad,#78h ; disable digital inputs on a/d input pins. anl p0m2,#87h ; disable digital outputs on a/d input pins. orl p0m1,#78h ; disable digital outputs on a/d input pins. following is an example of using the a/d with interrupts. the routine adstart begins an a/d conversion using the a/d channel number supplied in the accumulator. the channel number is not checked for validity. the a/d must previously have been enabled with suf?cient time to allow for stabilization. the interrupt handler routine reads the conversion value and returns it in memory address adresult. the interrupt should be enabled prior to starting the conversion. ; start a/d conversion. adstart: orl adcon,a ; add in the new channel number. setb adcs ; start an a/d conversion. ; orl pcon,#01h ; the cpu could be put into idle mode here. ; orl pcon,#02h ; the cpu could be put into power-down mode here if rcclk = 1. ret ; a/d interrupt handler. adint: push acc ; save accumulator. mov a,dac0 ; get a/d result, by reading dac0 sfr mov adresult,a ; and save it in memory. clr adci ; clear the a/d completion flag. anl adcon,#0fch ; clear the a/d channel number. pop acc ; restore accumulator. ret following is an example of using the a/d with polling. an a/d conversion is started using the channel number supplied in the accumulator. the channel number is not checked for validity. the a/d must previously have been enabled with suf?cient time to allow for stabilization. the conversion result is returned in the accumulator.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 17 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. adread: orl adcon,a ; add in the new channel number. setb adcs ; start a/d conversion. adchk: jnb adci,adchk ; wait for adci to be set. mov a,dac0 ; get a/d result. clr adci ; clear the a/d completion flag. anl adcon,#0fch ; clear the a/d channel number. ret 8.5 digital to analog converter (dac) outputs the P87LPC779 provides a two channel, 8-bit dac function. dac0 is also part of the a/d converter and is should not be enabled while the a/d is active. the dac outputs function down to a v dd of 3.0 v. digital outputs must be disabled on the dac output pins while the corresponding dac is enabled, as described in section 8.2 analog functions on page 12 . the dacs use the power supply as the references: v dd as the upper reference and vss as the lower reference. the dac output is generated by a tap from a resistor ladder and is not buffered. the maximum resistance to v dd or v ss from a dac output is 10 k w . care must be taken with the loading of the dac outputs in order to avoid distortion of the output voltage. dac accuracy is affected by noise generated on-chip and elsewhere in the application. since the P87LPC779 power pins are used for the dac references, the power supply also affects the accuracy of the dac outputs. the ideal dac output may be calculated as follows: (2) where dac value is the contents of the relevant dac register: dac0 or dac1. 8.6 analog comparators two analog comparators are provided on the P87LPC779. input and output options allow use of the comparators in a number of different con?gurations. comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the fig 6. dac block diagram. result dac value 0.5 + () v dd v ss C 256 ------------------------- - = d/a converter v ref + = v dd adcon dacn v ref - = v ss dacn pin endacn 002aaa817 (d/a conversion, write dacn)
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 18 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. negative input (selectable from a pin or an internal reference voltage). otherwise the output is a zero. each comparator may be con?gured to cause an interrupt when the output value changes. 8.6.1 comparator con?guration each comparator has a control register, cmp1 for comparator 1 and cmp2 for comparator 2. the control registers are identical and are shown in tables 9 and 10 . the overall connections to both comparators are shown in figure 7 . there are eight possible con?gurations for each comparator, as determined by the control bits in the corresponding cmpn register: cpn, cnn, and oen. these con?gurations are shown in figure 8 . the comparators function down to a v dd of 3.0 v. when each comparator is ?rst enabled, the comparator output and interrupt ?ag are not guaranteed to be stable for 10 m s. the corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt ?ag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. table 9: cmpn - comparator control registers cmp1 and cmp2 (address ach for cmp1, adh for cmp2) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - - cen cpn cnn oen con cmfn table 10: cmpn - comparator control registers cmp1 and cmp2 (address ach for cmp1, adh for cmp2) bit description bit symbol description 7, 6 - reserved for future use. should not be set to 1 by user programs. 5 cen comparator enable. when set by software, the corresponding comparator function is enabled. comparator output is stable 10 m s after cen is ?rst set. 4 cpn comparator positive input select. when 0, cinna is selected as the positive comparator input. when 1, cinnb is selected as the positive comparator input. 3 cnn comparator negative input select. when 0, the comparator reference pin cmpref is selected as the negative comparator input. when 1, the internal comparator reference vref is selected as the negative comparator input. 2 oen output enable. when 1, the comparator output is connected to the cmpn pin if the comparator is enabled (cen = 1). this output is asynchronous to the cpu clock. 1 con comparator output, synchronized to the cpu clock to allow reading by software. cleared when the comparator is disabled (cen = 0). 0 cmfn comparator interrupt ?ag. this bit is set by hardware whenever the comparator output con changes state. this bit will cause a hardware interrupt if enabled and of suf?cient priority. cleared by software and when the comparator is disabled (cen = 0).
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 19 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.6.2 internal reference voltage an internal reference voltage generator may supply a default reference when a single comparator input pin is used. the value of the internal reference voltage, referred to as vref, is 1.28 v 10 %. fig 7. comparator input and output connections. comparator 1 cp1 cn1 (p0.4) cin1a (p0.3) cin1b (p0.5) cmpref v ref oe1 change detect co1 cmf1 interrupt change detect cmf2 interrupt 002aaa617 cmp1 (p0.6) comparator 2 oe2 co2 cmp2 (p0.0) cp2 cn2 (p0.2) cin2a (p0.1) cin2b a. cpn, cnn, oe n=000 b. cpn, cnn, oe n=001 c. cpn, cnn, oe n=010 d. cpn, cnn, oe n=011 e. cpn, cnn, oe n=100 f. cpn, cnn, oe n=101 g. cpn, cnn, oe n=110 h. cpn, cnn, oe n=111 fig 8. comparator con?gurations. cinna cmpref 002aaa618 con cinna cmpref 002aaa620 con cmpn cinna v ref (1.23v) 002aaa621 con cinna v ref (1.23 v) 002aaa622 con cmpn cinnb cmpref 002aaa623 con cinnb cmpref 002aaa624 con cmpn cinnb v ref (1.23v) 002aaa625 con cinnb v ref (1.23 v) 002aaa626 con cmpn
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 20 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.6.3 comparator interrupt each comparator has an interrupt ?ag cmfn contained in its con?guration register. this ?ag is set whenever the comparator output changes state. the ?ag may be polled by software or may be used to generate an interrupt. the interrupt will be generated when the corresponding enable bit ecn in the ien1 register is set and the interrupt system is enabled via the ea bit in the ien0 register. 8.6.4 comparators and power reduction modes either or both comparators may remain enabled when power-down or idle mode is activated. the comparators will continue to function in the power reduction mode. if a comparator interrupt is enabled, a change of the comparator output state will generate an interrupt and wake up the processor. if the comparator output to a pin is enabled, the pin should be con?gured in the push-pull mode in order to obtain fast switching times while in power-down mode. the reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. comparators consume power in power-down and idle modes, as well as in the normal operating mode. this fact should be taken into account when system power consumption is an issue. 8.6.5 comparator con?guration example the code shown below is an example of initializing one comparator. comparator 1 is con?gured to use the cin1a and cmpref inputs, outputs the comparator result to the cmp1 pin, and generates an interrupt when the comparator output changes. cmpinit: b mov pt0ad,#30h ; disable digital inputs on pins that are used ; for analog functions: cin1a, cmpref. anl p0m2,#0cfh ; disable digital outputs on pins that are used orl p0m1,#30h ; for analog functions: cin1a, cmpref. mov cmp1,#24h ; turn on comparator 1 and set up for: ; - positive input on cin1a. ; - negative input from cmpref pin. ; - output to cmp1 pin enabled. call delay10us ; the comparator has to start up for at ; least 10 microseconds before use. anl cmp1,#0feh ; clear comparator 1 interrupt flag. setb ec1 ; enable the comparator 1 interrupt. the ; priority is left at the current value. setb ea ; enable the interrupt system (if needed). ret ; return to caller. the interrupt routine used for the comparator must clear the interrupt ?ag (cmf1 in this case) before returning. 8.7 i 2 c-bus serial interface the i 2 c-bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus are: ? bidirectional data transfer between masters and slaves. ? serial addressing of slaves (no added wiring).
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 21 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? acknowledgment after each transferred byte. ? multimaster bus. ? arbitration between simultaneously transmitting masters without corruption of serial data on bus. the i 2 c -bus subsystem includes hardware to simplify the software required to drive the i 2 c-bus. the hardware is a single bit interface which in addition to including the necessary arbitration and framing error checks, includes clock stretching and a bus timeout timer. the interface is synchronized to software either through polled loops or interrupts. refer to the application note an422, in section 4, entitled using the 8xc751 microcontroller as an i 2 c-bus master for additional discussion of the 87c77x i 2 c-bus interface and sample driver routines. six time spans are important in i 2 c-bus operation and are insured by timer i: ? the minimum high time for scl when this device is the master. ? the minimum low time for scl when this device is a master. this is not very important for a single-bit hardware interface like this one, because the scl low time is stretched until the software responds to the i 2 c-bus ?ags. the software response time normally meets or exceeds the min lo time. in cases where the software responds within min hi + min lo) time, timer i will ensure that the minimum time is met. ? the minimum scl high to sda high time in a stop condition. ? the minimum sda high to sda low time between i 2 c-bus stop and start conditions (4.7 ms, see i 2 c-bus speci?cation). ? the minimum sda low to scl low time in a start condition. the maximum scl change time while an i 2 c-bus frame is in progress. a frame is in progress between a start condition and the following stop condition. this time span serves to detect a lack of software response on this device as well as external i 2 c-bus problems. scl stuck low indicates a faulty master or slave. scl stuck high may mean a faulty device, or that noise induced onto the i 2 c-bus caused all masters to withdraw from i 2 c-bus arbitration. the ?rst ?ve of these times are 4.7 ms (see i 2 c-bus speci?cation) and are covered by the low order three bits of timer i. timer i is clocked by the 87lpc77987 cpu clock. timer i can be pre-loaded with one of four values to optimize timing for different oscillator frequencies. at lower frequencies, software response time is increased and will degrade maximum performance of the i 2 c-bus. see special function register i2cfg description for prescale values (ct0, ct1). the maximum scl change time is important, but its exact span is not critical. the complete 10 bits of timer i are used to count out the maximum time. when i 2 c-bus operation is enabled, this counter is cleared by transitions on the scl pin. the timer does not run between i 2 c-bus frames (i.e., whenever reset or stop occurred more recently than the last start). when this counter is running, it will carry out after 1020 to 1023 machine cycles have elapsed since a change on scl. a carry out causes a hardware reset of the i 2 c-bus interface. in cases where the bus hang-up is due to a lack of software response by this device, the reset releases scl and allows i 2 c-bus operation among other devices to continue.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 22 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.7.1 i 2 c-bus interrupts if i 2 c-bus interrupts are enabled (ea and ei2 are both set to 1), an i 2 c-bus interrupt will occur whenever the atn ?ag is set by a start, stop, arbitration loss, or data ready condition (refer to the description of atn following). in practice, it is not ef?cient to operate the i 2 c-bus interface in this fashion because the i 2 c-bus interrupt service routine would somehow have to distinguish between hundreds of possible conditions. also, since i 2 c-bus can operate at a fairly high rate, the software may execute faster if the code simply waits for the i 2 c-bus interface. typically, the i 2 c-bus interrupt should only be used to indicate a start condition at an idle slave device, or a stop condition at an idle master device (if it is waiting to use the i 2 c-bus). this is accomplished by enabling the i 2 c-bus interrupt only during the aforementioned conditions. [1] due to the manner in which bit addressing is implemented in the 80c51 family, the i2con register should never be altered by use of the setb, clr, cpl, mov (bit), or jbc instructions. this is due to the fact that read and write functions of this register are different. testing of i2con bits via the jb and jnb instructions is supported. table 11: i2con - i 2 c-bus control register (address d8h) bit allocation bit addressable [1] ; reset value: 81h bit 7 6 5 4 3 2 1 0 symbol (r) rdat atn drdy arl str stp master - symbol (w) cxa idle cdr carl cstr cstp xstr xstp table 12: i2con - i 2 c-bus control register (address d8h) bit description bit symbol access description 7 rdat r the most recently received data bit cxa w clears the transmit active ?ag 6 atn r atn = 1 if any of the ?ags drdy, arl, stp, or stp = 1 idle w in the i 2 c-bus slave mode, writing a 1 to this bit causes the i 2 c-bus hardware to ignore the bus until it is needed again 5 drdy r data ready ?ag, set when there is a rising edge on scl cdr w writing a 1 to this bit clears the drdy ?ag 4 arl r arbitration loss ?ag, set when arbitration is lost while in the transmit mode carl w writing a 1 to this bit clears the carl ?ag 3 str r start ?ag, set when a start condition is detected at a master or non-idle slave cstr w writing a 1 to this bit clears the str ?ag 2 stp r stop ?ag, set when a stop condition is detected at a master or non-idle slave cstp w writing a 1 to this bit clears the stp ?ag 1 master r indicates whether this device is currently as bus master xstr w writing a 1 to this bit causes a repeated start condition to be generated 0 - r unde?ned xstp w writing a 1 to this bit causes a stop condition to be generated
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 23 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.7.2 reading i2con rdat the data from sda is captured into receive data whenever a rising edge occurs on scl. rdat is also available (with seven low-order zeros) in the i2dat register. the difference between reading it here and there is that reading i2dat clears drdy, allowing the i 2 c-bus to proceed on to another bit. typically, the ?rst seven bits of a received byte are read from i2dat, while the 8th is read here. then i2dat can be written to send the acknowledge bit and clear drdy. atn attention is 1 when one or more of drdy, arl, str, or stp is 1. thus, atn comprises a single bit that can be tested to release the i 2 c-bus service routine from a wait loop. drdy data ready (and thus atn) is set when a rising edge occurs on scl, except at idle slave. drdy is cleared by writing cdr = 1, or by writing or reading the i2dat register. the following low period on scl is stretched until the program responds by clearing drdy. 8.7.3 checking atn and drdy when a program detects atn = 1, it should next check drdy. if drdy = 1, then if it receives the last bit, it should capture the data from rdat (in i2dat or i2con). next, if the next bit is to be sent, it should be written to i2dat. one way or another, it should clear drdy and then return to monitoring atn. note that if any of arl, str, or stp is set, clearing drdy will not release scl to high, so that the i 2 c-bus will not go on to the next bit. if a program detects atn = 1, and drdy = 0, it should go on to examine arl, str, and stp. arl arbitration loss is 1 when transmit active was set, but this device lost arbitration to another transmitter. transmit active is cleared when arl is 1. there are four separate cases in which arl is set: 1. if the program sent a 1 or repeated start, but another device sent a 0, or a stop, so that sda is 0 at the rising edge of scl. (if the other device sent a stop, the setting of arl will be followed shortly by stp being set.) 2. if the program sent a 1, but another device sent a repeated start, and it drove sda low before scl could be driven low. (this type of arl is always accompanied by str = 1.) 3. in master mode, if the program sent a repeated start, but another device sent a 1, and it drove scl low before this device could drive sda low. 4. in master mode, if the program sent stop, but it could not be sent because another device sent a 0. str start is set to a 1 when an i 2 c-bus start condition is detected at a non-idle slave or at a master. (str is not set when an idle slave becomes active due to a start bit; the slave has nothing useful to do until the rising edge of scl sets drdy.) stp stop is set to 1 when an i 2 c-bus stop condition is detected at a non-idle slave or at a master. (stp is not set for a stop condition at an idle slave.) master master is 1 if this device is currently a master on the i 2 c-bus. master is set when mastrq is 1 and the bus is not busy (i.e., if a start bit hasnt been received since reset or a timer i time-out, or if a stop has been received since the last start). master is cleared when arl is set, or after the software writes mastrq = 0 and then xstp = 1.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 24 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.7.4 writing i2con typically, for each bit in an i 2 c-bus message, a service routine waits for atn = 1. based on drdy, arl, str, and stp, and on the current bit position in the message, it may then write i2con with one or more of the following bits, or it may read or write the i2dat register. cxa writing a 1 to clear xmit active clears the transmit active state. (reading the i2dat register also does this.) 8.7.5 regarding transmit active transmit active is set by writing the i2dat register, or by writing i2con with xstr = 1 or xstp = 1. the i 2 c-bus interface will only drive the sda line low when transmit active is set, and the arl bit will only be set to 1 when transmit active is set. transmit active is cleared by reading the i2dat register, or by writing i2con with cxa = 1. transmit active is automatically cleared when arl is 1. idle writing 1 to idle causes a slaves i 2 c-bus hardware to ignore the i 2 c-bus until the next start condition (but if mastrq is 1, then a stop condition will cause this device to become a master). cdr writing a 1 to clear data ready' clears drdy. (reading or writing the i2dat register also does this.) carl writing a 1 to clear arbitration loss clears the arl bit. cstr writing a 1 to clear start clears the str bit. cstp writing a 1 to clear stop clears the stp bit. note that if one or more of drdy, arl, str, or stp is 1, the low time of scl is stretched until the service routine responds by clearing them. xstr writing 1s to xmit repeated start and cdr tells the i 2 c-bus hardware to send a repeated start condition. this should only be at a master. note that xstr need not and should not be used to send an initial (non-repeated) start; it is sent automatically by the i 2 c-bus hardware. writing xstr = 1 includes the effect of writing i2dat with xdat = 1; it sets transmit active and releases sda to high during the scl low time. after scl goes high, the i 2 c-bus hardware waits for the suitable minimum time and then drives sda low to make the start condition. xstp writing 1s to xmit stop and cdr tells the i 2 c-bus hardware to send a stop condition. this should only be done at a master. if there are no more messages to initiate, the service routine should clear the mastrq bit in i2cfg to 0 before writing xstp with 1. writing xstp = 1 includes the effect of writing i2dat with xdat = 0; it sets transmit active and drives sda low during the scl low time. after scl goes high, the i 2 c-bus hardware waits for the suitable minimum time and then releases sda to high to make the stop condition. table 13: i2dat - i 2 c-bus data register (address d9h) bit allocation not bit addressable; reset value: xxh bit 7 6 5 4 3 2 1 0 symbol (r) rdat------- symbol (w) xdat-------
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 25 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.7.6 regarding software response time because the P87LPC779 can run at 20 mhz, and because the i 2 c-bus interface is optimized for high-speed operation, it is quite likely that an i 2 c-bus service routine will sometimes respond to drdy (which is set at a rising edge of scl) and write i2dat before scl has gone low again. if xdat were applied directly to sda, this situation would produce an i 2 c-bus protocol violation. the programmer need not worry about this possibility because xdat is applied to sda only when scl is low. conversely, a program that includes an i 2 c-bus service routine may take a long time to respond to drdy. typically, an i 2 c-bus routine operates on a ?ag-polling basis during a message, with interrupts from other peripheral functions enabled. if an interrupt occurs, it will delay the response of the i 2 c-bus service routine. the programmer need not worry about this very much either, because the i 2 c-bus hardware stretches the scl low time until the service routine responds. the only constraint on the response is that it must not exceed the timer i time-out. table 14: i2dat - i 2 c-bus data register (address d9h) bit description bit symbol access description 7 rdat r the most recently received data bit, captured from sda at every rising edge of scl. reading i2dat also clears drdy and the transmit active state. xdat w sets the data for the next transmitted bit. writing i2dat also clears drdy and sets the transmit active state. 6 to 0 - - reserved for future use. should not be set to 1 by user programs. table 15: i2cfg - i 2 c-bus con?guration register (address c8h) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol slaven mastrq clrti tirun - - ct1 ct0 table 16: i2cfg - i 2 c-bus con?guration register (address c8h) bit description bit symbol description 7 slaven slave enable. writing a 1 this bit enables the slave functions of the i 2 c-bus subsystem. if slaven and mastrq are 0, the i 2 c-bus hardware is disabled. this bit is cleared to 0 by reset and by an i 2 c-bus time-out. 6 mastrq master request. writing a 1 to this bit requests mastership of the i 2 c-bus. if a transmission is in progress when this bit is changed from 0 to 1, action is delayed until a stop condition is detected. a start condition is sent and drdy is set (thus making atn = 1 and generating an i 2 c-bus interrupt). when a master wishes to release mastership status of the i 2 c-bus, it writes a 1 to xstp in i2con. mastrq is cleared by an i 2 c-bus time-out. 5 clrti writing a 1 to this bit clears the timer i over?ow ?ag. this bit position always reads as a 0.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 26 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. values to be used in the ct1 and ct0 bits are shown in ta b l e 1 8 . to allow the i 2 c-bus to run at the maximum rate for a particular oscillator frequency, compare the actual oscillator rate to the f osc max column in the table. the value for ct1 and ct0 is found in the ?rst line of the table where cpu clock max is greater than or equal to the actual frequency. ta b l e 1 8 also shows the machine cycle count for various settings of ct1/ct0. this allows calculation of the actual minimum high and low times for scl as follows: (3) for instance, at an 8 mhz frequency, with ct1/ct0 set to 1 0, the minimum scl high and low times will be 5.25 m s. ta b l e 1 8 also shows the timer i timeout period (given in machine cycles) for each ct1/ct0 combination. the timeout period varies because of the way in which minimum scl high and low times are measured. when the i 2 c-bus interface is operating, timer i is pre-loaded at every scl transition with a value dependent upon ct1/ct0. the pre-load value is chosen such that a minimum scl high or low time has elapsed when timer i reaches a count of 008 (the actual value pre-loaded into timer i is 8 minus the machine cycle count). 4 tirun writing a 1 to this bit lets timer i run; a 0 stops and clears it. together with slaven, mastrq, and master, this bit determines operational modes as shown in ta b l e 1 7 . 3, 2 - reserved for future use. should not be set to 1 by user programs. 1, 0 ct1, ct0 these two bits are programmed as a function of the cpu clock rate, to optimize the min hi and lo time of scl when this device is a master on the i 2 c-bus. the time value determined by these bits controls both of these parameters, and also the timing for stop and start conditions. table 17: interaction of tirun with slaven, mastrq, and master slaven, mastrq, master tirun operating mode all 0 0 the i 2 c-bus interface is disabled. timer i is cleared and does not run. this is the state assumed after a reset. if an i 2 c-bus application wants to ignore the i 2 c-bus at certain times, it should write slaven, mastrq, and tirun all to zero. all 0 1 the i 2 c-bus interface is disabled. any or all 1 0 the i 2 c-bus interface is enabled. the 3 low-order bits of timer i run for min-time generation, but the hi-order bits do not, so that there is no checking for i 2 c-bus being hung. this con?guration can be used for very slow i 2 c-bus operation. any or all 1 1 the i 2 c-bus interface is enabled. timer i runs during frames on the i 2 c-bus, and is cleared by transitions on scl, and by start and stop conditions. this is the normal state for i 2 c-bus operation. table 16: i2cfg - i 2 c-bus con?guration register (address c8h) bit description bit symbol description scl min high/low time (in microseconds) 6 * min time count cpuclock (in mhz) ------------------------------------------------ =
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 27 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.8 interrupts the P87LPC779 uses a four priority level interrupt structure. this allows great ?exibility in controlling the handling of the P87LPC779s many interrupt sources. the P87LPC779 supports up to 13 interrupt sources. each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers ien0 or ien1. the ien0 register also contains a global disable bit, ea, which disables all interrupts at once. each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the ip0, ip0h, ip1, and ip1h registers. an interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the highest priority interrupt service cannot be interrupted by any other interrupt source. so, if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. this is called the arbitration ranking. note that the arbitration ranking is only used to resolve simultaneous requests of the same priority level. ta b l e 1 9 summarizes the interrupt sources, ?ag bits, vector addresses, enable bits, priority bits, arbitration ranking, and whether each interrupt may wake up the cpu from power-down mode. table 18: ct1, ct0 values ct1, ct0 min time count (machine cycles) cpu clock max (for 100 khz i 2 c-bus) timeout period (machine cycles) 1 0 7 8.4 mhz 1023 0 1 6 7.2 mhz 1022 0 0 5 6.0 mhz 1021 1 1 4 4.8 mhz 1020 table 19: summary of interrupts description interrupt flag bit(s) vector address interrupt enable bit(s) interrupt priority arbitration ranking power-down wake-up external interrupt 0 ie0 0003h ex0 (ien0.0) ip0h.0, ip0.0 1 (highest) yes timer0 interrupt tf0 000bh et0 (ien0.1) ip0h.1, ip0.1 4 no external interrupt 1 ie1 0013h ex1 (ien0.2) ip0h.2, ip0.2 7 yes timer1 interrupt tf1 001bh et1 (ien0.3) ip0h.3, ip0.3 10 no serial port tx and rx ti & ri 0023h es (ien0.4) ip0h.4, ip0.4 12 no brownout detect bod 002bh ebo (ien0.5) ip0h.5, ip0.5 2 yes i 2 c-bus interrupt atn 0033h ei2 (ien1.0) ip1h.0, ip1.0 5 no kbi interrupt kbf 003bh ekb (ien1.1) ip1h.1, ip1.1 8 yes comparator 2 interrupt cmf2 0043h ec2 (ien1.2) ip1h.2, ip1.2 11 yes watchdog timer wdovf 0053h ewd (ien0.6) ip0h.6, ip0.6 3 yes
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 28 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.8.1 external interrupt inputs the P87LPC779 has two individual interrupt inputs as well as the keyboard interrupt function. the latter is described separately elsewhere in this section. the two interrupt inputs are identical to those present on the standard 80c51 microcontroller. the external sources can be programmed to be level-activated or transition-activated by setting or clearing bit it1 or it0 in register tcon. if itn = 0, external interrupt n is triggered by a detected low at the intn pin. if itn = 1, external interrupt n is edge triggered. in this mode if successive samples of the intn pin show a high in one cycle and a low in the next cycle, interrupt request ?ag ien in tcon is set, causing an interrupt request. since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 6 cpu clocks to ensure proper sampling. if the external interrupt is transition-activated, the external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle. this is to ensure that the transition is seen and that interrupt request ?ag ien is set. ien is automatically cleared by the cpu when the service routine is called. if the external interrupt is level-activated, the external source must hold the request active until the requested interrupt is actually generated. if the external interrupt is still asserted when the interrupt service routine is completed another interrupt will be generated. it is not necessary to clear the interrupt ?ag ien when the interrupt is level sensitive, it simply tracks the input pin level. if an external interrupt is enabled when the P87LPC779 is put into power-down or idle mode, the interrupt will cause the processor to wake up and resume operation. refer to section 8.12 power reduction modes on page 38 for details. a/d converter adci 005bh ead (ien1.4) ip1h.4, ip1.4 6 yes comparator 1 interrupt cmf1 0063h ec1 (ien1.5) ip1h.5, ip1.5 9 yes timer i interrupt - 0073h eti (ien1.7) ip1h.7, ip1.7 13 (lowest) no table 19: summary of interrupts continued description interrupt flag bit(s) vector address interrupt enable bit(s) interrupt priority arbitration ranking power-down wake-up
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 29 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.9 i/o ports the P87LPC779 has 3 i/o ports, port 0, port 1, and port 2. the exact number of i/o pins available depends upon the oscillator and reset options chosen. at least 15 pins of the P87LPC779 may be used as i/os when a two-pin external oscillator and an external reset circuit are used. up to 18 pins may be available if fully on-chip oscillator and reset con?gurations are chosen. all but three i/o port pins on the P87LPC779 may be software con?gured to one of four types on a bit-by-bit basis, as shown in ta b l e 2 0 . these are: quasi-bidirectional (standard 80c51 port outputs), push-pull, open drain, and input only. two con?guration registers for each port choose the output type for each port pin. 8.9.1 quasi-bidirectional output con?guration the default port output con?guration for standard P87LPC779 i/o ports is the quasi-bidirectional output that is common on the 80c51 and most of its derivatives. this output type can be used as both an input and output without the need to recon?gure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is fig 9. interrupt sources, interrupt enables, and power-down wake-up sources. 002aaa627 ie0 ex0 ie1 ex1 bod ebo kbf ekb interrupt to cpu wake-up (if in power- down) ec2 cm2 ewd wdt ead adc ec1 cm1 ea (from ie0 register) tf0 et0 tf1 et1 ri & ti es at n ei2 timer 1 interrupt eti table 20: port output con?guration settings pxm1.y pxm2.y port output mode 0 0 quasi-bidirectional 0 1 push-pull 1 0 input only (high impedance) 1 1 open drain
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 30 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. pulled low, it is driven strongly and able to sink a fairly large current. these features are somewhat similar to an open drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. one of these pull-ups, called the very weak pull-up, is turned on whenever the port latch for the pin contains a logic 1. the very weak pull-up sources a very small current that will pull the pin high if it is left ?oating. a second pull-up, called the weak pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. this pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. if a pin that has a logic 1 on it is pulled low by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and take the voltage on the port pin below its input threshold. the third pull-up is referred to as the strong pull-up. this pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. when this occurs, the strong pull-up turns on for a brief time, two cpu clocks, in order to pull the port pin high quickly. then it turns off again. the quasi-bidirectional port con?guration is shown in figure 10 . 8.9.2 open drain output con?guration the open drain output con?guration turns off all pull-ups and only drives the pulldown transistor of the port driver when the port latch contains a logic 0. to be used as a logic output, a port con?gured in this manner must have an external pull-up, typically a resistor tied to v dd . the pulldown for this mode is the same as for the quasi-bidirectional mode. the open drain port con?guration is shown in figure 11 . fig 10. quasi-bidirectional output. 002aaa628 2 cpu clock delay port latch data weak strong input data very weak pp p n v dd port pin
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 31 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.9.3 push-pull output con?guration the push-pull output con?guration has the same pulldown structure as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. the push-pull port con?guration is shown in figure 12 . the three port pins that cannot be con?gured are p1.2, p1.3, and p1.5. the port pins p1.2 and p1.3 are permanently con?gured as open drain outputs. they may be used as inputs by writing ones to their respective port latches. p1.5 may be used as a schmitt trigger input if the P87LPC779 has been con?gured for an internal reset and is not using the external reset input function rst. additionally, port pins p2.0 and p2.1 are disabled for both input and output if one of the crystal oscillator options is chosen. those options are described in section 8.10 oscillator on page 34 . fig 11. open drain output. 002aaa629 port latch data input data n port pin fig 12. push-pull output. 002aaa630 port latch data input data n port pin p v dd
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 32 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. the value of port pins at reset is determined by the prhi bit in the ucfg1 register. ports may be con?gured to reset high or low as needed for the application. when port pins are driven high at reset, they are in quasi-bidirectional mode and therefore do not source large amounts of current. every output on the P87LPC779 may potentially be used as a 20 ma sink led drive output. however, there is a maximum total output current for all ports which must not be exceeded. all ports pins of the P87LPC779 have slew rate controlled outputs. this is to limit noise generated by quickly switching output signals. the slew rate is factory set to approximately 10 ns rise and fall times. the bits in the p2m1 register that are not used to control con?guration of p2.1 and p2.0 are used for other purposes. these bits can enable schmitt trigger inputs on each i/o port, enable toggle outputs from timer 0 and timer 1, and enable a clock output if either the internal rc oscillator or external clock input is being used. the last two functions are described in section 8.14 timer/counters on page 41 and section 8.10 oscillator on page 34 respectively. the enable bits for all of these functions are shown in tables 21 and 22 . each i/o port of the P87LPC779 may be selected to use ttl level inputs or schmitt inputs with hysteresis. a single con?guration bit determines this selection for the entire port. port pins p1.2, p1.3, and p1.5 always have a schmitt trigger input. table 21: p2m1 - port 2 mode register 1 (address a4h) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol p2s p1s p0s enclk ent1 ent0 (p2m1.1) (p2m1.0) table 22: p2m1 - port 2 mode register 1 (address a4h) bit description bit symbol description 7 p2s when p2s = 1, this bit enables schmitt trigger inputs on port 2. 6 p1s when p1s = 1, this bit enables schmitt trigger inputs on port 1. 5 p0s when p0s = 1, this bit enables schmitt trigger inputs on port 0. 4 enclk when enclk is set and the P87LPC779 is con?gured to use the on-chip rc oscillator, a clock output is enabled on the x2 pin (p2.0). refer to section 8.10 oscillator on page 34 for details. 3 ent1 when set, the p.7 pin is toggled whenever timer1 over?ows. the output frequency is therefore one half of the timer1 over?ow rate. refer to section 8.14 timer/counters on page 41 for details. 2 ent0 when set, the p1.2 pin is toggled whenever timer0 over?ows. the output frequency is therefore one half of the timer0 over?ow rate. refer to section 8.14 timer/counters on page 41 for details. 1, 0 - these bits, along with the matching bits in the p2m2 register, control the output con?guration of p2.1 and p2.0 respectively, as shown in ta b l e 2 0 .
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 33 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.9.4 keyboard interrupt (kbi) the keyboard interrupt function is intended primarily to allow a single interrupt to be generated when any key is pressed on a keyboard or keypad connected to speci?c pins of the P87LPC779, as shown in figure 13 . this interrupt may be used to wake up the cpu from idle or power-down modes. this feature is particularly useful in handheld, battery powered systems that need to carefully manage power consumption yet also need to be convenient to use. the P87LPC779 allows any or all pins of port 0 to be enabled to cause this interrupt. port pins are enabled by the setting of bits in the kbi register, as shown in tables 23 and 24 . the keyboard interrupt flag (kbf) in the auxr1 register is set when any enabled pin is pulled low while the kbi interrupt function is active. an interrupt will be generated if it has been enabled. note that the kbf bit must be cleared by software. due to human time scales and the mechanical delay associated with keyswitch closures, the kbi feature will typically allow the interrupt service routine to poll port 0 in order to determine which key was pressed, even if the processor has to wake up from power-down mode. refer to section 8.12 power reduction modes on page 38 for details. fig 13. keyboard interrupt. table 23: kbi - keyboard interrupt register (address 86h) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol kbi.7 kbi.6 kbi.5 kbi.4 kbi.3 kbi.2 kbi.1 kbi.0 002aaa631 p0.7 kbi.7 p0.6 kbi.6 p0.5 kbi.5 p0.4 kbi.4 p0.3 kbi.3 p0.2 kbi.2 p0.1 kbi.1 p0.0 kbi.0 kbf (kbi interrupt) ekb (from ien1 register)
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 34 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.10 oscillator the P87LPC779 provides several user selectable oscillator options, allowing optimization for a range of needs from high precision to lowest possible cost. these are con?gured when the eprom is programmed. basic oscillator types that are supported include: low, medium, and high speed crystals, covering a range from 20 khz to 20 mhz; ceramic resonators; and on-chip rc oscillator. 8.10.1 low speed oscillator option this option supports an external crystal in the range of 20 khz to 100 khz. 8.10.2 medium speed oscillator option this option supports an external crystal in the range of 100 khz to 4 mhz. ceramic resonators are also supported in this con?guration. 8.10.3 high speed oscillator option this option supports an external crystal in the range of 4 mhz to 20 mhz. ceramic resonators are also supported in this con?guration. table 24: kbi - keyboard interrupt register (address 86h) bit description bit symbol description 7 - when set, enables p0.7 as a cause of a keyboard interrupt. 6 - when set, enables p0.6 as a cause of a keyboard interrupt. 5 - when set, enables p0.5 as a cause of a keyboard interrupt. 4 - when set, enables p0.4 as a cause of a keyboard interrupt. 3 - when set, enables p0.3 as a cause of a keyboard interrupt. 2 - when set, enables p0.2 as a cause of a keyboard interrupt. 1 - when set, enables p0.1 as a cause of a keyboard interrupt. 0 - when set, enables p0.0 as a cause of a keyboard interrupt. table 25: recommended oscillator capacitors for use with the low frequency oscillator option oscillator frequency v dd = 2.7 v to 4.5 v v dd = 4.5 v to 6.0 v lower limit optimal value upper limit lower limit optimal value upper limit 20 khz 15 pf 15 pf 33 pf 33 pf 33 pf 47 pf 32 khz 15 pf 15 pf 33 pf 33 pf 33 pf 47 pf 100 khz 15 pf 15 pf 33 pf 15 pf 15 pf 33 pf table 26: recommended oscillator capacitors for use with the medium frequency oscillator option oscillator frequency v dd = 2.7 v to 4.5 v v dd = 4.5 v to 6.0 v lower limit optimal value upper limit lower limit optimal value upper limit 100 khz 33 pf 33 pf 47 pf 33 pf 33 pf 47 pf 1 mhz 15 pf 15 pf 33 pf 15 pf 22 pf 47 pf 4 mhz 15 pf 15 pf 33 pf 15 pf 15 pf 33 pf
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 35 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.10.4 on-chip rc oscillator option the on-chip rc oscillator option has a typical frequency of 6 mhz and can be divided down for slower operation through the use of the divm register. a clock output on the x2 / p2.0 pin may be enabled when the on-chip rc oscillator is used. 8.10.5 external clock input option in this con?guration, the processor clock is input from an external source driving the x1 / p2.1 pin. the rate may be from 0 hz up to 20 mhz when v dd is above 4.5 v and up to 10 mhz when v dd is below 4.5 v. when the external clock input mode is used, the x2 / p2.0 pin may be used as a standard port pin. a clock output on the x2 / p2.0 pin may be enabled when the external clock input is used. 8.10.6 clock output the P87LPC779 supports a clock output function when either the on-chip rc oscillator or external clock input options are selected. this allows external devices to synchronize to the P87LPC779. when enabled, via the enclk bit in the p2m1 register, the clock output appears on the x2 / clkout pin whenever the on-chip oscillator is running, including in idle mode. the frequency of the clock output is 1 6 of the cpu clock rate. if the clock output is not needed in idle mode, it may be turned off prior to entering idle, saving additional power. the clock output may also be enabled when the external clock input option is selected. table 27: recommended oscillator capacitors for use with the high frequency oscillator option oscillator frequency v dd = 2.7 v to 4.5 v v dd = 4.5 v to 6.0 v lower limit optimal value upper limit lower limit optimal value upper limit 4 mhz 15 pf 33 pf 47 pf 15 pf 33 pf 68 pf 8 mhz 15 pf 15 pf 33 pf 15 pf 33 pf 47 pf 16 mhz - - - 15 pf 15 pf 33 pf 20 mhz - - - 15 pf 15 pf 33 pf the oscillator must be con?gured in one of the following modes: low frequency crystal, medium frequency crystal, or high frequency crystal. (1) a series resistor may be required to limit crystal drive levels. this is especially important for low frequency crystals (see text). fig 14. using the crystal oscillator. 002aaa632 87lpc77x x1 x2 quartz crystal or ceramic resonator [1]
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 36 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.10.7 cpu clock modi?cation: clkr and divm for backward compatibility, the clkr con?guration bit allows setting the P87LPC779 instruction and peripheral timing to match standard 80c51 timing by dividing the cpu clock by two. default timing for the P87LPC779 is 6 cpu clocks per machine cycle while standard 80c51 timing is 12 clocks per machine cycle. this division also applies to peripheral timing, allowing 80c51 code that is oscillator frequency and/or timer rate dependent. the clkr bit is located in the eprom con?guration register ucfg1, described under section 8.18 eprom characteristics on page 61 . the oscillator must be con?gured in the external clock input mode. a clock output may be obtained on the x2 pin by setting the enclk bit in the p2m1 register. fig 15. using an external clock input. 002aaa633 87lpc778 x1 x2 cmos compatible external oscillator signal fig 16. block diagram of oscillator control. 002aaa634 fosc2 (ucfg1.2) fosc1 (ucfg1.1) fosc0 (ucfg1.0) clock select xtal select clock out clock sources external clock input internal rc oscillator crystal: low frequency crystal: medium frequency crystal: high frequency power monitor reset power down 10-bit ripple counter oscillator startup timer divide-by-m (divm register) and clkr select count 256 clkr (ucfg1.3) reset count count 1024 ? 1 / ? 2 cpu clock
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 37 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. in addition to this, the cpu clock may be divided down from the oscillator rate by a programmable divider, under program control. this function is controlled by the divm register. if the divm register is set to zero (the default value), the cpu will be clocked by either the unmodi?ed oscillator rate, or that rate divided by two, as determined by the previously described clkr function. when the divm register is set to some value n (between 1 and 255), the cpu clock is divided by 2 (n + 1). clock division values from 4 through 512 are thus possible. this feature makes it possible to temporarily run the cpu at a lower rate, reducing power consumption, in a manner similar to idle mode. by dividing the clock, the cpu can retain the ability to respond to events other than those that can cause interrupts (i.e., events that allow exiting the idle mode) by executing its normal program at a lower rate. this can allow bypassing the oscillator startup time in cases where power-down mode would otherwise be used. the value of divm may be changed by the program at any time without interrupting code execution. 8.11 power monitoring functions the P87LPC779 incorporates power monitoring functions designed to prevent incorrect operation during initial power up and power loss or reduction during operation. this is accomplished with two hardware functions: power-on detect and brownout detect. 8.11.1 brownout detection the brownout detect function helps prevent the processor from failing in an unpredictable manner if the power supply voltage drops below a certain level. the default operation is for a brownout detection to cause a processor reset, however it may alternatively be con?gured to generate an interrupt by setting the boi bit in the auxr1 register (auxr1.5). the P87LPC779 allows selection of two brownout levels: 2.5 v or 3.8 v. when v dd drops below the selected voltage, the brownout detector triggers and remains active until v dd is returns to a level above the brownout detect voltage. when brownout detect causes a processor reset, that reset remains active as long as v dd remains below the brownout detect voltage. when brownout detect generates an interrupt, that interrupt occurs once as v dd crosses from above to below the brownout detect voltage. for the interrupt to be processed, the interrupt system and the boi interrupt must both be enabled (via the ea and ebo bits in ien0). when brownout detect is activated, the bof ?ag in the pcon register is set so that the cause of processor reset may be determined by software. this ?ag will remain set until cleared by software. for correct activation of brownout detect, the v dd fall time must be no faster than 50 mv/ m s. when v dd is restored, is should not rise faster than 2 mv/ m s in order to insure a proper reset. the brownout voltage (2.5 v or 3.8 v) is selected via the bov bit in the eprom con?guration register ucfg1. when unprogrammed (bov = 1), the brownout detect voltage is 2.5 v. when programmed (bov = 0), the brownout detect voltage is 3.8 v.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 38 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. if the brownout detect function is not required in an application, it may be disabled, thus saving power. brownout detect is disabled by setting the control bit bod in the auxr1 register (auxr1.6). 8.11.2 power-on detection the power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. when this feature is activated, the pof ?ag in the pcon register is set to indicate an initial power up condition. the pof ?ag will remain set until cleared by software. 8.12 power reduction modes the P87LPC779 supports idle and power-down modes of power reduction. 8.12.1 idle mode the idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. any enabled interrupt source or reset may terminate idle mode. idle mode is entered by setting the idl bit in the pcon register (see tables 29 and 30 ). 8.12.2 power-down mode the power-down mode stops the oscillator in order to absolutely minimize power consumption. power-down mode is entered by setting the pd bit in the pcon register (see tables 29 and 30 ). the processor can be made to exit power-down mode via reset or one of the interrupt sources shown in ta b l e 2 8 . this will occur if the interrupt is enabled and its priority is higher than any interrupt currently in progress. in power-down mode, the power supply voltage may be reduced to the ram keep-alive voltage v ram . this retains the ram contents at the point where power-down mode was entered. sfr contents are not guaranteed after v dd has been lowered to v ram , therefore it is recommended to wake up the processor via reset in this case. v dd must be raised to within the operating range before the power-down mode is exited. since the watchdog timer has a separate oscillator, it may reset the processor upon over?ow if it is running during power-down. note that if the brownout detect reset is enabled, the processor will be put into reset as soon as v dd drops below the brownout voltage. if brownout detect is con?gured as an interrupt and is enabled, it will wake up the processor from power-down mode when v dd drops below the brownout voltage. when the processor wakes up from power-down mode, it will start the oscillator immediately and begin execution when the oscillator is stable. oscillator stability is determined by counting 1024 cpu clocks after start-up when one of the crystal oscillator con?gurations is used, or 256 clocks after start-up for the internal rc or external clock input con?gurations.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 39 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. some chip functions continue to operate and draw power during power-down mode, increasing the total power used during power-down. these include the brownout detect, watchdog timer, and comparators. 8.12.3 low voltage eprom operation the eprom array contains some analog circuits that are not required when v dd is less than 4 v, but are required for a v dd greater than 4 v. the lpep bit (auxr.4), when set by software, will power-down these analog circuits resulting in a reduced supply current. lpep is cleared only by power-on reset, so it may be set only for applications that always operate with v dd less than 4 v. table 28: interrupt sources wake-up source conditions external interrupt 0 or 1 the corresponding interrupt must be enabled. keyboard interrupt the keyboard interrupt feature must be enabled and properly set up. the corresponding interrupt must be enabled. comparator 1 or 2 the comparator(s) must be enabled and properly set up. the corresponding interrupt must be enabled. watchdog timer reset the watchdog timer must be enabled via the wdte bit in the ucfg1 eprom con?guration byte. watchdog timer interrupt the wdte bit in the ucfg1 eprom con?guration byte must not be set. the corresponding interrupt must be enabled. brownout detect reset the bod bit in auxr1 must not be set (brownout detect not disabled). the boi bit in auxr1 must not be set (brownout interrupt disabled). brownout detect interrupt the bod bit in auxr1 must not be set (brownout detect not disabled). the boi bit in auxr1 must be set (brownout interrupt enabled). the corresponding interrupt must be enabled. reset input the external reset input must be enabled. a/d converter must use internal rc clock (rcclk = 1) for a/d converter to work in power-down mode. the a/d must be enabled and properly set up. the corresponding interrupt must be enabled. table 29: pcon - power control register (address 87h) bit allocation not bit addressable; reset value: 30h for a power-on reset; 20h for a brownout reset; 00h for other reset sources. bit 7 6 5 4 3 2 1 0 symbol smod1 smod0 bof pof gf1 gf0 pd idl table 30: pcon - power control register (address 87h) bit description bit symbol description 7 smod1 when set, this bit doubles the uart baud rate for modes 1, 2, and 3. 6 smod0 this bit selects the function of bit 7 of the scon sfr. when 0, scon.7 is the sm0 bit. when 1, scon.7 is the fe (framing error) ?ag. see tables 36 and 37 for additional information. 5 bof brown out flag. set automatically when a brownout reset or interrupt has occurred. also set at power-on. cleared by software. refer to section 8.11 power monitoring functions on page 37 for additional information.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 40 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.13 reset the P87LPC779 has an active low reset input when con?gured for an external reset. a fully internal reset may also be con?gured which provides a reset when power is initially applied to the device. the watchdog timer can act as an oscillator fail detect because it uses an independent, fully on-chip oscillator. the external reset input is disabled, and fully internal reset generation enabled, by programming the rpd bit in the eprom con?guration register ucfg1 to 0. eprom con?guration is described in section 8.18 eprom characteristics on page 61 . 4 pof power-on flag. set automatically when a power-on reset has occurred. cleared by software. refer to the section 8.11 power monitoring functions on page 37 for additional information. 3 gf1 general purpose ?ag 1. may be read or written by user software, but has no effect on operation. 2 gf0 general purpose ?ag 0. may be read or written by user software, but has no effect on operation. 1 pd power-down control bit. setting this bit activates power-down mode operation. cleared when the power-down mode is terminated (see text). 0 idl idle mode control bit. setting this bit activates idle mode operation. cleared when the idle mode is terminated (see text). table 30: pcon - power control register (address 87h) bit description continued bit symbol description fig 17. typical external reset circuits. 002aaa857 87lpc779 p1.5 87lpc779 rst
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 41 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.14 timer/counters the P87LPC779 has two general purpose counter/timers which are upward compatible with the standard 80c51 timer0 and timer1. both can be con?gured to operate either as timers or event counters (see tables 31 and 32 ). an option to automatically toggle the t0 and/or t1 pins upon timer over?ow has been added. in the timer function, the register is incremented every machine cycle. thus, one can think of it as counting machine cycles. since a machine cycle consists of 6 cpu clock periods, the count rate is 1 6 of the cpu clock frequency. refer to section 8.1 enhanced cpu on page 12 for a description of the cpu clock. in the counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t0 or t1. in this function, the external input is sampled once during every machine cycle. when the samples of the pin state show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register during the cycle following the one in which the transition was detected. since it takes 2 machine cycles (12 cpu clocks) to recognize a 1-to-0 transition, the maximum count rate is 1 6 of the cpu clock frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. the timer or counter function is selected by control bits c/t in the special function register tmod. in addition to the timer or counter selection, timer0 and timer1 have four operating modes, which are selected by bit-pairs (m1, m0) in tmod. modes 0, 1, and 2 are the same for both timers/counters. mode 3 is different. the four operating modes are described in the following text. fig 18. block diagram showing reset sources. 002aaa636 rpd (ucfg1.6) rst / v pp pin wdte (ucfg1.7) wdt module software reset srst (auxr1.3) power monitor reset s q chip reset r reset timing cpu clock
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 42 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.14.1 mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. figure 19 shows mode 0 operation. in this mode, the timer register is con?gured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt ?ag tfn. the count input is enabled to the timer when trn = 1 and either gate = 0 or intn = 1. (setting gate = 1 allows the timer to be controlled by external input intn, to facilitate pulse width measurements). trn is a control bit in the special function register tcon (tables 34 and 35 ). the gate bit is in the tmod register. the 13-bit register consists of all 8 bits of thn and the lower 5 bits of tln. the upper 3 bits of tln are indeterminate and should be ignored. setting the run ?ag (trn) does not clear the registers. mode 0 operation is the same for timer0 and timer1. see figure 19 . there are two different gate bits, one for timer1 (tmod.7) and one for timer0 (tmod.3). table 31: tmod - timer/counter mode control register (address 89h) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol gate c/ tm1 m0gatec/ tm1 m0 table 32: tmod - timer/counter mode control register (address 89h) bit description bit symbol description 7 gate gating control for timer1. when set, timer/counter is enabled only while the int1 pin is high and the tr1 control pin is set. when cleared, timer1 is enabled when the tr1 control bit is set. 6c/ t timer or counter selector for timer1. cleared for timer operation (input from internal system clock.) set for counter operation (input from t1 input pin). 5, 4 m1, m0 mode select for timer1 (see table below). 3 gate gating control for timer0. when set, timer/counter is enabled only while the int0 pin is high and the tr0 control pin is set. when cleared, timer0 is enabled when the tr0 control bit is set. 2c/ t timer or counter selector for timer0. cleared for timer operation (input from internal system clock.) set for counter operation (input from t0 input pin). 1, 0 m1, m0 mode select for timer0 (see ta b l e 3 3 below). table 33: m1, m0 timer mode m1, m0 timer mode 0 0 8048 timer tln serves as 5-bit prescaler. 0 1 16-bit timer/counter thn and tln are cascaded; there is no prescaler. 1 0 8-bit auto-reload timer/counter. thn holds a value which is loaded into tln when it over?ows. 1 1 timer0 is a dual 8-bit timer/counter in this mode. tl0 is an 8-bit timer/counter controlled by the standard timer0 control bits. th0 is an 8-bit timer only, controlled by the timer1 control bits (see text). timer1 in this mode is stopped.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 43 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.14.2 mode 1 mode 1 is the same as mode 0, except that all 16 bits of the timer register (thn and tln) are used. see figure 20 . 8.14.3 mode 2 mode 2 con?gures the timer register as an 8-bit counter (tl1) with automatic reload, as shown in figure 21 . over?ow from tln not only sets tfn, but also reloads tln with the contents of thn, which must be preset by software. the reload leaves thn unchanged. mode 2 operation is the same for timer0 and timer1. 8.14.4 mode 3 when timer1 is in mode 3 it is stopped. the effect is the same as setting tr1 = 0. timer0 in mode 3 establishes tl0 and th0 as two separate 8-bit counters. the logic for mode 3 on timer0 is shown in figure 22 . tl0 uses the timer0 control bits: c/t, gate, tr0, int0, and tf0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer1. thus, th0 now controls the timer1 interrupt. mode 3 is provided for applications that require an extra 8-bit timer. with timer0 in mode 3, an P87LPC779 can look like it has three timer/counters. when timer0 is in mode 3, timer1 can be turned on and off by switching it into and out of its own mode 3. it can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt. table 34: tcon - timer/counter control register (address 88h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 table 35: tcon - timer/counter control register (address 88h) bit description bit symbol description 7 tf1 timer1 over?ow ?ag. set by hardware on timer/counter over?ow. cleared by hardware when the interrupt is processed, or by software. 6 tr1 timer1 run control bit. set/cleared by software to turn timer/counter 1 on/off. 5 tf0 timer0 over?ow ?ag. set by hardware on timer/counter over?ow. cleared by hardware when the processor vectors to the interrupt routine, or by software. 4 tr0 timer0 run control bit. set/cleared by software to turn timer/counter 0 on/off. 3 ie1 interrupt 1 edge ?ag. set by hardware when external interrupt 1 edge is detected. cleared by hardware when the interrupt is processed, or by software.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 44 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 2 it1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. 1 ie0 interrupt 0 edge ?ag. set by hardware when external interrupt 0 edge is detected. cleared by hardware when the interrupt is processed, or by software. 0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. table 35: tcon - timer/counter control register (address 88h) bit description bit symbol description fig 19. timer/counter 0 or 1 in mode 0 (13-bit counter). 002aaa637 osc/6 or osc/12 tn pin trn gate intn pin c/t = 0 c/t = 1 tln (5-bits) thn (8-bits) tfn control tnoe tn pin toggle overflow interrupt fig 20. timer/counter 0 or 1 in mode 1 (16-bit counter). 002aaa638 osc/6 or osc/12 tn pin trn gate intn pin c/t = 0 c/t = 1 tln (8-bits) thn (8-bits) tfn control tnoe tn pin toggle overflow interrupt fig 21. timer/counter 0 or 1 in mode 2 (8-bit auto-reload). 002aaa639 osc/6 or osc/12 tn pin trn gate intn pin c/t = 0 c/t = 1 tln (8-bits) thn (8-bits) tfn control tine tn pin toggle overflow interrupt reload
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 45 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.14.5 timer over?ow toggle output timers 0 and 1 can be con?gured to automatically toggle a port output whenever a timer over?ow occurs. the same device pins that are used for the t0 and t1 count inputs are also used for the timer toggle outputs. this function is enabled by control bits ent0 and ent1 in the p2m1 register, and apply to timer0 and timer1 respectively. the port outputs will be a logic 1 prior to the ?rst timer over?ow when this mode is turned on. 8.15 uart the P87LPC779 includes an enhanced 80c51 uart. the baud rate source for the uart is timer1 for modes 1 and 3, while the rate is ?xed in modes 0 and 2. because cpu clocking is different on the P87LPC779 than on the standard 80c51, baud rate calculation is somewhat different. enhancements over the standard 80c51 uart include framing error detection and automatic address recognition. the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the sbuf register. however, if the ?rst byte still hasnt been read by the time reception of the second byte is complete, the ?rst byte will be lost. the serial port receive and transmit registers are both accessed through special function register sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the serial port can be operated in 4 modes. fig 22. timer/counter 0 mode 3 (two 8-bit counters). 002aaa640 osc/6 or osc/12 osc/6 or osc/12 t0 pin tr0 tr1 gate int0 pin c/t = 0 c/t = 1 tl0 (8-bits) tf0 control t0oe t0 pin toggle overflow interrupt th0 (8-bits) tf1 control t1oe t1 pin toggle overflow interrupt
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 46 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.15.1 mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted or received, lsb ?rst. the baud rate is ?xed at 1 6 of the cpu clock frequency. 8.15.2 mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb ?rst), and a stop bit (logic 1). when data is received, the stop bit is stored in rb8 in special function register scon. the baud rate is variable and is determined by the timer1 over?ow rate. 8.15.3 mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logic 0), 8 data bits (lsb ?rst), a programmable 9th data bit, and a stop bit (logic 1). when data is transmitted, the 9th data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. when data is received, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1 16 or 1 32 of the cpu clock frequency, as determined by the smod1 bit in pcon. 8.15.4 mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb ?rst), a programmable 9th data bit, and a stop bit (logic 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable and is determined by the timer1 over?ow rate. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren=1. 8.15.5 serial port control register (scon) the serial port control and status register is the special function register scon, shown in tables 36 and 37 . this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri). the framing error bit (fe) allows detection of missing stop bits in the received data stream. the fe bit shares the bit position scon.7 with the sm0 bit. which bit appears in scon at any particular time is determined by the smod0 bit in the pcon register. if smod0 = 0, scon.7 is the sm0 bit. if smod0 = 1, scon.7 is the fe bit. once set, the fe bit remains set until it is cleared by software. this allows detection of framing errors for a group of characters without the need for monitoring it for every character individually. table 36: scon - serial port control register (address 98h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol fe/sm0 sm1 sm2 ren tb8 rb8 ti ri
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 47 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.15.6 baud rates the baud rate in mode 0 is ?xed: mode 0 baud rate = cpu clock/6. the baud rate in mode 2 depends on the value of bit smod1 in special function register pcon. if smod1 = 0 (which is the value on reset), the baud rate is 1 32 of the cpu clock frequency. if smod1 = 1, the baud rate is 1 16 of the cpu clock frequency. (4) table 37: scon - serial port control register (address 98h) bit description bit symbol description 7 fe framing error. this bit is set by the uart receiver when an invalid stop bit is detected. must be cleared by software. the smod0 bit in the pcon register must be 1 for this bit to be accessible. see sm0 bit below. sm0 with sm1, de?nes the serial port mode. the smod0 bit in the pcon register must be 0 for this bit to be accessible. see fe bit above. 6 sm1 with sm0, de?nes the serial port mode (see ta b l e 3 8 below). 5 sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1, then rl will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2 = 1 then ri will not be activated if a valid stop bit was not received. in mode 0, sm2 should be 0. 4 ren enables serial reception. set by software to enable reception. clear by software to disable reception. 3 tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. 2 rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, it sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. 1 ti transmit interrupt ?ag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. 0 ri receive interrupt ?ag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. table 38: sm0, sm1 serial port mode sm0, sm1 uart mode baud rate 0 0 0: shift register cpu clock/6 0 1 1: 8-bit uart variable (see text) 1 0 2: 9-bit uart cpu clock/32 or cpu clock/16 1 1 3: 9-bit uart variable (see text) mode 2 baud rate 1 smod1 + 32 ----------------------------- - cpu clock frequency =
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 48 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.15.7 using timer1 to generate baud rates when timer1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer1 over?ow rate and the value of smod1. the timer1 interrupt should be disabled in this application. the timer itself can be con?gured for either timer or counter operation, and in any of its 3 running modes. in the most typical applications, it is con?gured for timer operation, in the auto-reload mode (high nibble of tmod = 0010b). in that case the baud rate is given by the formula: (5) tables 39 and 40 list various commonly used baud rates and how they can be obtained using timer1 as the baud rate generator. mode 1, 3 baud rate cpu clock frequency / 192 (or 96 if smod 1 = 1) 256 th 1 () C ------------------------------------------------------------------------------------------------------------------------ - = table 39: baud rates, timer values, and cpu clock frequencies for smod1 = 0 timer count baud rate 2400 4800 9600 19.2 k 38.4 k 57.6 k - 1 0.4608 0.9216 * 1.8432 * 3.6864 * 7.3728 * 11.0592 - 2 0.9216 1.8432 * 3.6864 * 7.3728 * 14.7456 - 3 1.3824 2.7648 5.5296 * 11.0592 - - - 4 * 1.8432 * 3.6864 * 7.3728 * 14.7456 - - - 5 2.3040 4.6080 9.2160 * 18.4320 - - - 6 2.7648 5.5296 * 11.0592 - - - - 7 3.2256 6.4512 12.9024 - - - - 8 * 3.6864 * 7.3728 * 14.7456 - - - - 9 4.1472 8.2944 16.5888 - - - - 10 4.6080 9.2160 * 18.4320 - - - table 40: baud rates, timer values, and cpu clock frequencies for smod1 = 1 timer value baud rate 2400 4800 9600 19.2 k 38.4 k 57.6 k 115.2 k - 1 0.2304 0.4608 0.9216 * 1.8432 * 3.6864 5.5296 * 11.0592 - 2 0.4608 0.9216 * 1.8432 * 3.6864 * 7.3728 * 11.0592 - - 3 0.6912 1.3824 2.7648 5.5296 * 11.0592 16.5888 - - 4 0.9216 * 1.8432 * 3.6864 * 7.3728 * 14.7456 - - - 5 1.1520 2.3040 4.6080 9.2160 * 18.4320 - - - 6 1.3824 2.7648 5.5296 * 11.0592 - - - - 7 1.6128 3.2256 6.4512 12.9024 - - - - 8 * 1.8432 * 3.6864 * 7.3728 * 14.7456 - - - - 9 2.0736 4.1472 8.2944 16.5888 - - - - 10 2.3040 4.6080 9.2160 * 18.4320 - - - - 11 2.5344 5.0688 10.1376 - - - - - 12 2.7648 5.5296 * 11.0592 - - - - - 13 2.9952 5.9904 11.9808 - - - - - 14 3.2256 6.4512 12.9024 - - - -
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 49 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] tables 39 and 40 apply to uart modes 1 and 3 (variable rate modes), and show cpu clock rates in mhz for standard baud rates from 2400 to 115.2 kbaud. [2] ta bl e 3 9 shows timer settings and cpu clock rates with the smod1 bit in the pcon register = 0 (the default after reset), while ta b l e 4 0 re?ects the smod1 bit = 1. [3] the tables show all potential cpu clock frequencies up to 20 mhz that may be used for baud rates from 9600 baud to 115.2 kbaud . other cpu clock frequencies that would give only lower baud rates are not shown. [4] table entries marked with an asterisk (*) indicate standard crystal and ceramic resonator frequencies that may be obtained f rom many sources without special ordering. 8.15.8 more about uart mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received: 8 data bits (lsb ?rst). the baud rate is ?xed at 1 6 the cpu clock frequency. figure 23 shows a simpli?ed functional diagram of the serial port in mode 0, and associated timing. transmission is initiated by any instruction that uses sbuf as a destination register. the write to sbuf signal at s6p2 also loads a 1 into the 9th position of the transmit shift register and tells the tx control block to commence a transmission. the internal timing is such that one full machine cycle will elapse between write to sbuf and activation of send. send enables the output of the shift register to the alternate output function line of p3.0 and also enable shift clock to the alternate output function line of p3.1. shift clock is low during s3, s4, and s5 of every machine cycle, and high during s6, s1, and s2. at s6p2 of every machine cycle in which send is active, the contents of the transmit shift are shifted to the right one position. as data bits shift out to the right, zeros come in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the msb, and all positions to the left of that contain zeros. this condition ?ags the tx control block to do one last shift and then deactivate send and set t1. both of these actions occur at s1p1 of the 10th machine cycle after write to sbuf. reception is initiated by the condition ren = 1 and r1 = 0. at s6p2 of the next machine cycle, the rx control unit writes the bits 11111110 t o the receive shift register, and in the next clock phase activates receive. - 15 3.4560 6.9120 13.8240 - - - - - 16 * 3.6864 * 7.3728 * 14.7456 - - - - - 17 3.9168 7.8336 15.6672 - - - - - 18 4.1472 8.2944 16.5888 - - - - - 19 4.3776 8.7552 17.5104 - - - - - 20 4.6080 9.2160 * 18.4320 - - - - - 21 4.8384 9.6768 19.3536 - - - - table 40: baud rates, timer values, and cpu clock frequencies for smod1 = 1 continued timer value baud rate 2400 4800 9600 19.2 k 38.4 k 57.6 k 115.2 k
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 50 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. receive enable shift clock to the alternate output function line of p3.1. shift clock makes transitions at s3p1 and s6p1 of every machine cycle. at s6p2 of every machine cycle in which receive is active, the contents of the receive shift register are shifted to the left one position. the value that comes in from the right is the value that was sampled at the p3.0 pin at s5p2 of the same machine cycle. as data bits come in from the right, 1s shift out to the left. when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it ?ags the rx control block to do one last shift and load sbuf. at s1p1 of the 10th machine cycle after the write to scon that cleared ri, receive is cleared as ri is set. 8.15.9 more about uart mode 1 ten bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb ?rst), and a stop bit (1). on receive, the stop bit goes into rb8 in scon. in the P87LPC779 the baud rate is determined by the timer1 over?ow rate. figure 24 shows a simpli?ed functional diagram of the serial port in mode 1, and associated timings for transmit receive. transmission is initiated by any instruction that uses sbuf as a destination register. the write to sbuf signal also loads a 1 into the 9th bit position of the transmit shift register and ?ags the tx control unit that a transmission is requested. transmission actually commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the write to sbuf signal.) the transmission begins with activation of send which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the ?rst shift pulse occurs one bit time after that. as data bits shift out to the right, zeros are clocked in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the msb, and all positions to the left of that contain zeros. this condition ?ags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 10th divide-by-16 rollover after write to sbuf. reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written into the input shift register. resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16ths. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the ?rst bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. this is to provide rejection of false start bits. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 51 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it ?ags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the ?nal shift pulse is generated: 1. r1 = 0, and 2. either sm2 = 0, or the received stop bit = 1. if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf, and ri is activated. at this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in rxd. 8.15.10 more about uart modes 2 and 3 eleven bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb ?rst), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8) can be assigned the value of 0 or 1. on receive, the 9th data bit goes into rb8 in scon. the baud rate is programmable to either 1 16 or 1 32 of the cpu clock frequency in mode 2. mode 3 may have a variable baud rate generated from timer1. figures 25 and 26 show a functional diagram of the serial port in modes 2 and 3. the receive portion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. transmission is initiated by any instruction that uses sbuf as a destination register. the write to sbuf signal also loads tb8 into the 9th bit position of the transmit shift register and ?ags the tx control unit that a transmission is requested. transmission commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the write to sbuf signal.) the transmission begins with activation of send, which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the ?rst shift pulse occurs one bit time after that. the ?rst shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. thereafter, only zeros are clocked in. thus, as data bits shift out to the right, zeros are clocked in from the left. when tb8 is at the output position of the shift register, then the stop bit is just to the left of tb8, and all positions to the left of that contain zeros. this condition ?ags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 11th divide-by-16 rollover after write to sbuf. reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written to the input shift register. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of r-d. the value accepted is the value that was seen in at least 2 of the 3 samples. if the value accepted during the ?rst bit time is not 0, the receive circuits are
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 52 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. reset and the unit goes back to looking for another 1-to-0 transition. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it ?ags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the ?nal shift pulse is generated. 1. ri = 0, and 2. either sm2 = 0, or the received 9th data bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. if both conditions are met, the received 9th data bit goes into rb8, and the ?rst 8 data bits go into sbuf. one bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the rxd input. 8.15.11 multiprocessor communications uart modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received or transmitted. when data is received, the 9th bit is stored in rb8. the uart can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. one way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it ?rst sends out an address byte which identi?es the target slave. an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that follow. the slaves that werent being addressed leave their sm2 bits set and go on about their business, ignoring the subsequent data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit, although this is better done with the framing error ?ag. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 8.15.12 automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt ?ag (ri) will be automatically set when the received byte contains either the given address or the broadcast address. the 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 53 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to de?ne the slaves address, saddr, and the address mask, saden. saden is used to de?ne which bits in the saddr are to be used and which bits are dont care. the saden mask can be logically anded with the saddr to create the given address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme: in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are treated as dont-cares. in most cases, interpreting the dont-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr and saden are loaded with 0s. this produces a given address of all dont cares as well as a broadcast address of all dont cares. this effectively disables the automatic addressing mode and allows the microcontroller to use standard uart drivers which do not make use of this feature. table 41: slave 0/1 examples example 1 example 2 slave 0 saddr = 1100 0000 slave 1 saddr = 1100 0000 saden = 1111 1101 saden = 1111 1110 given = 1100 00x0 given = 1100 000x table 42: slave 0/1/2 examples example 1 example 2 example 3 slave 0 saddr = 1100 0000 slave 1 saddr = 1110 0000 slave 2 saddr = 1110 0000 saden = 1111 1001 saden = 1111 1010 saden = 1111 1100 given = 1100 0xx0 given = 1110 0x0x given = 1110 00xx
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 54 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 23. serial port mode 0. 80c51 internal bus 002aaa641 80c51 internal bus write to sbuf sbuf zero detector rxd p3.0 alt output function tx control s tx clock start q cl d serial port interrupt shift clock shift send s6 rxd p3.0 alt input function load sbuf ti input shift register start ri receive shift tx clock rx control ren ri sbuf read sbuf transmit txd p3.1 alt output function send rxd (data out) rxd (data in) d0 d1 d5 d2 d6 d3 d4 d7 txd (shift clock) shift s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 write to sbuf ti receive receive d0 d1 d5 d2 d6 d3 d4 d7 txd (shift clock) shift write to scon (clear ri) ri 11 111 11 0
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 55 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 24. serial port mode 1. 80c51 internal bus sbuf zero detector txd tx control s tx clock start q cl d serial port interrupt shift send load sbuf ti input shift register start ri load sbuf shift rx clock 1ffh rx control sbuf read sbuf transmit rxd p3.0 alt input function 80c51 internal bus data tb8 ? 16 ? 16 ? 2 timer 1 overflow smod1 = 0 smod1 = 1 1-to-0 transition detector bit detector start bit stop bit tx clock write to sbuf send data shift txd ti d0 d1 d5 d2 d6 d3 d4 d7 receive rx clock shift ri bit detector sample times start bit stop bit rxd d0 d1 d5 d2 d6 d3 d4 d7 write to sbuf 002aaa642 ? 16 reset
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 56 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 25. serial port mode 2. 80c51 internal bus sbuf zero detector txd tx control s tx clock start stop bit gen q cl d serial port interrupt shift send load sbuf ti input shift register start ri load sbuf shift rx clock 1ffh rx control sbuf read sbuf transmit rxd p3.0 alt input function 80c51 internal bus data tb8 ? 16 ? 16 ? 2 phase 2 clock (1/2 f osc ) smod1 = 0 smod1 = 1 1-to-0 transition detector bit detector start bit stop bit stop bit tx clock write to sbuf send data shift txd ti stop bit gen d0 d1 d5 d2 d6 d3 d4 d7 receive rx clock shift ri bit detector sample times start bit rxd d0 d1 d5 d2 d6 d3 d4 d7 write to sbuf 002aaa643 tb8 rb8 ? 16 reset
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 57 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 26. serial port mode 3. 80c51 internal bus sbuf zero detector txd tx control s tx clock start q cl d serial port interrupt shift send load sbuf ti input shift register start ri load sbuf shift rx clock 1ffh rx control sbuf read sbuf transmit rxd p3.0 alt input function 80c51 internal bus data tb8 ? 16 ? 16 ? 2 timer 1 overflow smod1 = 0 smod1 = 1 1-to-0 transition detector bit detector start bit stop bit stop bit tx clock write to sbuf send data shift txd ti stop bit gen d0 d1 d5 d2 d6 d3 d4 d7 receive rx clock shift ri bit detector sample times start bit rxd d0 d1 d5 d2 d6 d3 d4 d7 write to sbuf 002aaa644 tb8 rb8 ? 16 reset
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 58 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.16 watchdog timer when enabled via the wdte con?guration bit, the watchdog timer is operated from an independent, fully on-chip oscillator in order to provide the greatest possible dependability. when the watchdog feature is enabled, the timer must be fed regularly by software in order to prevent it from resetting the cpu, and it cannot be turned off. when disabled as a watchdog timer (via the wdte bit in the ucfg1 con?guration register), it may be used as an interval timer and may generate an interrupt. the watchdog timer is shown in figure 27 . the watchdog timeout time is selectable from one of eight values, nominal times range from 16 milliseconds to 2.1 seconds. the frequency tolerance of the independent watchdog rc oscillator is 37 %. the timeout selections and other control bits are shown in tables 43 and 44 . when the watchdog function is enabled, the wdcon register may be written once during chip initialization in order to set the watchdog timeout time. the recommended method of initializing the wdcon register is to ?rst feed the watchdog, then write to wdcon to con?gure the wds2-0 bits. using this method, the watchdog initialization may be done any time within 10 milliseconds after start-up without a watchdog over?ow occurring before the initialization can be completed. since the watchdog timer oscillator is fully on-chip and independent of any external oscillator circuit used by the cpu, it intrinsically serves as an oscillator fail detection function. if the watchdog feature is enabled and the cpu oscillator fails for any reason, the watchdog timer will time out and reset the cpu. when the watchdog function is enabled, the timer is deactivated temporarily when a chip reset occurs from another source, such as a power-on reset, brownout reset, or external reset. fig 27. block diagram of the watchdog timer. 002aaa645 500 khz r/c oscillator clock out enable wdclk * wdte wdte + wdrun state clock 20-bit counter clear 8 msbs wds2-0 (wdcon.2-0) wdte (ucfg1.7) watchdog reset watchdog interrupt wdovf (wdcon.5) watchdog feed detect bod (xxx.x) por (xxx.x) s r q 8 to 1 mux
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 59 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.16.1 watchdog feed sequence if the watchdog timer is running, it must be fed before it times out in order to prevent a chip reset from occurring. the watchdog feed sequence consists of ?rst writing the value 1eh, then the value e1h to the wdrst register. an example of a watchdog feed sequence is shown below. wdfeed: mov wdrst,#1eh ; first part of watchdog feed sequence. mov wdrst,#0e1h ; second part of watchdog feed sequence. the two writes to wdrst do not have to occur in consecutive instructions. an incorrect watchdog feed sequence does not cause any immediate response from the watchdog timer, which will still time out at the originally scheduled time if a correct feed sequence does not occur prior to that time. after a chip reset, the user program has a limited time in which to either feed the watchdog timer or change the timeout period. when a low cpu clock frequency is used in the application, the number of instructions that can be executed before the watchdog over?ows may be quite small. 8.16.2 watchdog reset if a watchdog reset occurs, the internal reset is active for approximately one microsecond. if the cpu clock was still running, code execution will begin immediately after that. if the processor was in power-down mode, the watchdog reset will start the oscillator and code execution will resume after the oscillator is stable. table 43: wdcon - watchdog timer control register (address a7h) bit allocation not bit addressable; reset value: 30h for a watchdog reset; 10h for other reset sources if the watchdog is enabled via the wdte con?guration bit; 00h for other reset sources if the watchdog is disabled via the wdte con?guration bit. bit 7 6 5 4 3 2 1 0 symbol - - wdovf wdrun wdclk wds2 wds1 wds0 table 44: wdcon - watchdog timer control register (address a7h) bit description bit symbol description 7, 6 - reserved for future use. should not be set to 1 by user programs. 5 wdovf watchdog timer over?ow ?ag. set when a watchdog reset or timer over?ow occurs. cleared when the watchdog is fed. 4 wdrun watchdog run control. the watchdog timer is started when wdrun = 1 and stopped when wdrun = 0. this bit is forced to 1 (watchdog running) if the wdte con?guration bit = 1. 3 wdclk watchdog clock select. the watchdog timer is clocked by cpu clock / 6 when wdclk = 1 and by the watchdog rc oscillator when wdclk = 0. this bit is forced to 0 (using the watchdog rc oscillator) if the wdte con?guration bit = 1. 2-0 wds2-0 watchdog rate select.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 60 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.17 additional features the auxr1 register contains several special purpose control bits that relate to several chip features. auxr1 is described in tables 46 and 47 . table 45: watchdog rate select clock time wds2-0 timeout clocks minimum time nominal time maximum time 0 0 0 8,192 10 ms 16 ms 23 ms 0 0 1 16,384 20 ms 32 ms 45 ms 0 1 0 32,768 41 ms 65 ms 90 ms 0 1 1 65,536 82 ms 131 ms 180 ms 1 0 0 131,072 165 ms 262 ms 360 ms 1 0 1 262,144 330 ms 524 ms 719 ms 1 1 0 524,288 660 ms 1.05 sec 1.44 sec 1 1 1 1,048,576 1.3 sec 2.1 sec 2.9 sec table 46: auxr1 - auxr1 register (address a2h) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol kbf bod boi lpep srst 0 - dps table 47: auxr1 - auxr1 register (address a2h) bit description bit symbol description 7 kbf keyboard interrupt flag. set when any pin of port 0 that is enabled for the keyboard interrupt function goes low. must be cleared by software. 6 bod brown out disable. when set, turns off brownout detection and saves power. see section 8.11 power monitoring functions on page 37 for details. 5 boi brown out interrupt. when set, prevents brownout detection from causing a chip reset and allows the brownout detect function to be used as an interrupt. see section 8.11 power monitoring functions on page 37 for details. 4 lpep low power eprom control bit. allows power savings in low voltage systems. set by software. can only be cleared by power-on or brownout reset. see section 8.12 power reduction modes on page 38 for details. 3 srst software reset. when set by software, resets the P87LPC779 as if a hardware reset occurred. 2 0 this bit contains a hard-wired 0. allows toggling of the dps bit by incrementing auxr1, without interfering with other bits in the register. 1 - reserved for future use. should not be set to 1 by user programs. 0 dps data pointer select. chooses one of two data pointers for use by the program. see text for details.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 61 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.17.1 software reset the srst bit in auxr1 allows software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. if a value is written to auxr1 that contains a 1 at bit position 3, all sfrs will be initialized and execution will resume at program address 0000. care should be taken when writing to auxr1 to avoid accidental software resets. 8.17.2 dual data pointers the dual data pointer (dptr) adds to the ways in which the processor can specify the address used with certain instructions. the dps bit in the auxr1 register selects one of the two data pointers. the dptr that is not currently selected is not accessible to software unless the dps bit is toggled. speci?c instructions affected by the data pointer selection are: ? inc dptr: increments the data pointer by 1. ? jmp @a+dptr: jump indirect relative to dptr value. ? mov dptr, #data16: load the data pointer with a 16-bit constant. ? movca, @a+dptr: move code byte relative to dptr to the accumulator. ? movxa, @dptr: move data byte the accumulator to data memory relative to dptr. ? movx @dptr, a: move data byte from data memory relative to dptr to the accumulator. also, any instruction that reads or manipulates the dph and dpl registers (the upper and lower bytes of the current dptr) will be affected by the setting of dps. the movx instructions have limited application for the P87LPC779 since the part does not have an external data bus. however, they may be used to access eprom con?guration information (see section 8.18 eprom characteristics ). bit 2 of auxr1 is permanently wired as a logic 0. this is so that the dps bit may be toggled (thereby switching data pointers) simply by incrementing the auxr1 register, without the possibility of inadvertently altering other bits in the register. 8.18 eprom characteristics programming of the eprom on the P87LPC779 is accomplished with a serial programming method. commands, addresses, and data are transmitted to and from the device on two pins after programming mode is entered. serial programming allows easy implementation of in-circuit programming of the P87LPC779 in an application board. the P87LPC779 contains three signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes designate the device as an P87LPC779 manufactured by philips. the signature bytes may be read by the user program at addresses fc30h, fc31h and fc60h with the movc instruction, using the dptr register for addressing.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 62 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. a special user data area is also available for access via the movc instruction at addresses fce0h through fcffh. this customer code space is programmed in the same manner as the main code eprom and may be used to store a serial number, manufacturing date, or other application information. 8.18.1 system con?guration bytes a number of user con?gurable features of the P87LPC779 must be de?ned at power up and therefore cannot be set by the program after start of execution. those features are con?gured through the use of two eprom bytes that are programmed in the same manner as the eprom program space. the contents of the two con?guration bytes, ucfg1 and ucfg2, are shown in tables 48 , 49 , 51 and 52 . the values of these bytes may be read by the program through the use of the movx instruction at the addresses shown in the tables. table 48: ucfg1 - eprom system con?guration byte 1 register (address fd00h) bit allocation unprogrammed value: ffh bit 7 6 5 4 3 2 1 0 symbol wdte rpd prhi bov clkr fosc2 fosc1 fosc0 table 49: ucfg1 - eprom system con?guration byte 1 register (address fd00h) bit description bit symbol description 7 wdte watchdog timer enable. when programmed (0), disables the watchdog timer. the timer may still be used to generate an interrupt. 6 rpd reset pin disable. when programmed (0), disables the reset function of pin p1.5, allowing it to be used as an input only port pin. 5 prhi port reset high. when 1, ports reset to a high state. when 0, ports reset to a low state. 4 bov brownout voltage select. when 1, the brownout detect voltage is 2.5 v. when 0, the brownout detect voltage is 3.8 v. this is described in section 8.11 power monitoring functions on page 37 . 3 clkr clock rate select. when 0, the cpu clock rate is divided by 2. this results in machine cycles taking 12 cpu clocks to complete as in the standard 80c51. for full backward compatibility, this division applies to peripheral timing as well. 2 to 0 fosc[2:0] cpu oscillator type select. see section 8.10 oscillator on page 34 for additional information. combinations other than those shown below should not be used. they are reserved for future use. table 50: fosc2-fosc0 oscillator con?guration fosc2-fosc0 oscillator con?guration 1 1 1 external clock input on x1 (default setting for an unprogrammed part). 0 1 1 internal rc oscillator, 6 mhz.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 63 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.18.2 security bits when neither of the security bits are programmed, the code in the eprom can be veri?ed. when only security bit 1 is programmed, all further programming of the eprom is disabled. at that point, only security bit 2 may still be programmed. when both security bits are programmed, eprom verify is also disabled. 0 1 0 low frequency crystal, 20 khz to 100 khz. 0 0 1 medium frequency crystal or resonator, 100 khz to 4 mhz. 0 0 0 high frequency crystal or resonator, 4 mhz to 20 mhz. table 51: ucfg2 - eprom system con?guration byte 2 register (address fd01h) bit allocation unprogrammed value: ffh bit 7 6 5 4 3 2 1 0 symbol sb2 sb1 - - - - - - table 52: ucfg2 - eprom system con?guration byte 2 register (address fd01h) bit description bit symbol description 7, 6 sb2, sb1 eprom security bits. see ta b l e 5 3 for details. 5-0 - reserved for future use. table 50: fosc2-fosc0 oscillator con?guration continued fosc2-fosc0 oscillator con?guration table 53: eprom security bits sb2 sb1 protection description 1 1 both security bits unprogrammed. no program security features enabled. eprom is programmable and veri?able. 1 0 only security bit 1 programmed. further eprom programming is disabled. security bit 2 may still be programmed. 0 1 only security bit 2 programmed. this combination is not supported. 0 0 both security bits programmed. all eprom veri?cation and programming are disabled.
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 64 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9. limiting values [1] stresses above those listed under table 54 limiting values may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in table 55 dc electrical characteristics and table 57 ac electrical characteristics of this speci?cation are not implied. [2] this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated max imum. [3] parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. table 54: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit t amb(bias) operating bias ambient temperature - 55 +85 c t stg storage temperature range - 65 +150 c v rst voltage on rst/v pp pin to v ss - +11.0 v v n voltage on any other pin to v ss - 0.5 v dd + 0.5 v i ol(i/o) low-level output current per i/o pin - 50 ma i oh(i/o) high-level output current per i/o pin - - 50 ma i ol(tot)(max) maximum total i ol for all outputs - 200 ma i oh(tot)(max) maximum total i oh for all outputs - - 200 ma p tot(pack) total power dissipation per package based on package heat transfer, not device power consumption - 1.5 w
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 65 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. static characteristics table 55: dc electrical characteristics v dd = 2.7 v to 5.5 v unless otherwise speci?ed. t amb = - 40 c to +85 c for extended industrial, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit i dd power supply current, operating 5.0 v; 20 mhz [10] -1525ma 3.0 v; 10 mhz [10] -47ma i id power supply current, idle mode 5.0 v; 20 mhz [10] - 6 10 ma 3.0 v; 10 mhz [10] -24ma i pd power supply current, power-down mode 5.0 v [10] -110 m a 3.0 v [10] -15 m a v ram ram keep-alive voltage 1.5 - - v v il low-level input voltage (ttl input) 4.5 v < v dd < 6.0 v - 0.5 - 0.2v dd - 0.1 v v il1 negative-going threshold (schmitt input) - 0.5 - 0.3v dd v v ih high-level input voltage (ttl input) 0.2v dd + 0.9 - v dd + 0.5 v v ih1 positive-going threshold (schmitt input) 0.7v dd -v dd + 0.5 v v hys hysteresis voltage - 0.2v dd -v v ol low-level output voltage; all ports [4][8] i ol = 3.2 ma; v dd = 4.5 v - - 0.4 v v ol1 low-level output voltage; all ports [4][8] i ol =20ma; v dd = 4.5 v - - 1.0 v v oh high-level output voltage, all ports [2] i oh = - 30 m a; v dd = 4.5 v v dd - 0.7 - - v v oh1 high-level output voltage, all ports [3] i oh = - 1.0 ma; v dd = 4.5 v v dd - 0.7 - - v c io input/output pin capacitance [9] - - 15 pf i il logic 0 input current, all ports [7] v in = 0.4 v - - - 50 m a i li input leakage current, all ports [6] v in =v il or v ih -- 2 m a i tl logic 1-to-0 transition current, all ports [2][5] v in = 2.0 v at v dd = 5.5 v - 150 - - 650 m a r rst internal reset pull-up resistor 40 - 225 k w
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 66 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] typical ratings are not guaranteed. the values listed are at room temperature, 5 v. [2] ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). does not apply to open-drain p ins. [3] ports in push-pull mode. does not apply to open drain pins. [4] in all output modes except high impedance mode. [5] port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. this curr ent is highest when v in is approximately 2 v. [6] measured with port in high-impedance mode. parameter is guaranteed, but not tested at cold temperature. [7] measured with port in quasi-bidirectional mode. [8] under steady state (non-transient conditions, i ol must be externally limited as follows. a) maximum i ol per port pin: 20 ma b) maximum i ol for all outputs: 80 ma c) maximum i ol for all outputs: 5 ma if i ol exceeds the test condition, v ol may exceed the related speci?cation. pins are not guaranteed to sink current greater than the listed test conditions. [9] pin capacitance is characterized but not tested. [10] the i dd , i id , and i pd speci?cations are measured using an external clock with the following functions disabled: comparators, brownout detect, and watchdog timer. for v dd = 3 v, lpep = 1. refer to the appropriate ?gure on the following pages for additional current drawn by each of these functions. [11] devices initially operating at v dd = 2.7 v or above and f osc = 10 mhz or less are guaranteed to continue to execute instructions correctly at the brownout trip point. initial power-on operation below v dd = 2.7 v is not guaranteed. [12] devices initially operating at v dd = 4.0 v or above and f osc = 20 mhz or less are guaranteed to continue to execute instructions correctly at the brownout trip point. initial power-on operation below v dd = 4.0 v and f osc > 10 mhz is not guaranteed v bolow brownout trip voltage with bov = 1 [11] 2.35 - 2.69 v v bohi brownout trip voltage with bov = 0 [12] 3.45 3.8 3.99 v v ref bandgap reference voltage 1.11 1.26 1.41 v table 55: dc electrical characteristics continued v dd = 2.7 v to 5.5 v unless otherwise speci?ed. t amb = - 40 c to +85 c for extended industrial, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 67 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] conditions: v ss =0v; v dd = 5.12 v. [2] the a/d is monotonic, there are no missing codes. [3] the differential non-linearity (dl e ) is the difference between the actual step width and the ideal step width. see figure 28 . [4] the integral non-linearity (il e ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 28 . [5] the offset error (os e ) is the absolute difference between the straight line which ?ts the actual transfer curve (after removing gain error), and the straight line which ?ts the ideal transfer curve. see figure 28 . [6] the gain error (g e ) is the relative difference in percent between the straight line ?tting the actual transfer curve (after removing offset error), and the straight line which ?ts the ideal transfer curve. gain error is constant at every point on the transfer curve. see figure 28 . [7] the absolute voltage error (a e ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. [8] this should be considered when both analog and digital signals are input simultaneously to a/d pins. [9] changing the input voltage faster than this may cause erroneous readings. [10] a source impedance higher than this driving an a/d input may result in loss of precision and erroneous readings. table 56: a/d converter dc electrical characteristics v dd = 2.7 v to 5.5 v unless otherwise speci?ed. t amb = - 40 c to +85 c for extended industrial, unless otherwise speci?ed. symbol parameter conditions min max unit av in analog input voltage v ss - 0.2 v dd + 0.2 v c ia analog input capacitance - 15 pf dl e differential non-linearity [1][2][3] - 1 lsb il e integral non-linearity [1][4] - 1 lsb os e offset error [1][5] - 1 lsb g e gain error [1][6] - 0.4 % a e absolute voltage error [1][7] - 1 lsb m ctc channel-to-channel matching - 1 lsb c t crosstalk between inputs of port [8] 0 to 100 khz - - 60 db - input slew rate - 100 v/ms - input source impedance - 10 k w
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 68 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential non-linearity (dl e ). (4) integral non-linearity (il e ). (5) center of a step of the actual transfer curve. fig 28. a/d conversion characteristics. 002aaa646 255 254 253 252 251 (2) (1) 256 250 251 252 253 254 255 7 123456 7 6 5 4 3 2 1 0 250 (5) (4) (3) 1 lsb (ideal) code out v dd - v ss 256 offset error os e gain error g e offset error os e av in (lsb ideal ) 1 lsb =
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 69 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. dynamic characteristics [1] applies only to an external clock source, not when a crystal is connected to the x1 and x2 pins. [2] tested at v dd = 5.0 v and room temperature. [3] these parameters are characterized but not tested. [4] these parameters are for 0 c to +70 c table 57: ac electrical characteristics v dd = 2.7 v to 5.5 v unless otherwise speci?ed; v ss = 0 v. [1][2][3] t amb = - 40 c to +85 c for extended industrial, unless otherwise speci?ed. symbol figure parameter min max unit external clock f c 30 oscillator frequency (v dd = 4.0 v to 6.0 v) 0 20 mhz f c 30 oscillator frequency (v dd = 2.7 v to 6.0 v) 0 10 mhz t c 30 clock period and cpu timing cycle 1/f c -ns t clcx 30 clock low-time [1] f osc = 20 mhz 20 - ns t clcx 30 f osc = 10 mhz 40 - ns t chcx 30 clock high time [1] f osc = 20 mhz 20 - ns t chcx 30 f osc = 10 mhz 40 - ns internal rc oscillator f ccal on-chip oscillator calibration [2] f rcosc = 6 mhz - 1+1% f ctol on-chip oscillator tolerance [3][4] f rcosc = 6 mhz - 2.5 +2.5 % f ctol1 on-chip oscillator tolerance [3] f rcosc = 6 mhz - 25 +25 % shift register t xlxl 29 serial port clock cycle time 6t c -ns t qvxh 29 output data setup to clock rising edge 5t c - 133 - ns t xhqx 29 output data hold after clock rising edge 1t c - 80 - ns t xhdv 29 input data setup to clock rising edge - 5t c - 133 ns t xhdx 29 input data hold after clock rising edge 0 - ns fig 29. shift register mode timing. 0 1234567 valid valid valid valid valid valid valid valid t xlxl 002aaa425 set ti set ri t xhqx t qvxh t xhdv t xhdx clock output data write to sbuf input data clear ri
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 70 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. comparator electrical characteristics [1] this parameter is characterized, but not tested in production. 13. d/a electrical characteristics fig 30. external clock timing. t chcl t clcx t chcx t c t clch 002aaa416 0.2 v dd + 0.9 0.2 v dd - 0.1 v v dd - 0.5 v 0.45 v table 58: comparator electrical characteristics v dd = 2.7 v to 5.5 v unless otherwise speci?ed. t amb = - 40 c to +85 c for extended industrial, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit v io offset voltage comparator inputs [1] -- 10 mv v cr common mode range comparator inputs 0 - v dd - 0.3 v cmrr common mode rejection ratio [1] -- - 50 db response time - 250 500 ns comparator enable to output valid - - 10 m s i il input leakage current, comparator 0 < v in < v dd -- 10 m a table 59: d/a electrical characteristics v dd = 2.7 v to 5.5 v unless otherwise speci?ed. t amb = - 40 c to +85 c for extended industrial, unless otherwise speci?ed. symbol parameter conditions min typ max unit analog output v oa output voltage no resistive load v ss -v dd v r l = 100 k 0.975 v dd -v dd v r l = 10 k 0.9 v dd -v dd v t dacrise rise time 10 % to 90 % v dd no load - 100 - ns c l = 100 pf - 500 - ns t dacfall fall time 90 % to 10 % v dd no load - 80 - ns c l = 100 pf - 500 - ns
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 71 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14. package outline fig 31. sot360-1. unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 110 20 11 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller product data rev. 02 03 may 2004 72 of 74 9397 750 13213 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15. revision history table 60: revision history rev date cpcn description 02 20040503 - product data (9397 750 13213) modi?cations: ? section 2 features on page 1 ; adjusted text 28-bit digital to analog converter to two 8-bit digital to analog converters. 01 20040405 - product data (9397 750 12976)
9397 750 13213 philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 02 03 may 2004 73 of 74 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 16. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 18. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 19. licenses level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c speci?cation de?ned by philips. this speci?cation can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004. printed in the u.s.a. all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 03 may 2004 document order number: 9397 750 13213 contents philips semiconductors P87LPC779 cmos single-chip 8-bit microcontroller 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 special function registers . . . . . . . . . . . . . . . . . 8 8 functional description . . . . . . . . . . . . . . . . . . 12 8.1 enhanced cpu . . . . . . . . . . . . . . . . . . . . . . . . 12 8.2 analog functions . . . . . . . . . . . . . . . . . . . . . . . 12 8.3 analog to digital converter . . . . . . . . . . . . . . . 12 8.4 a/d timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.4.1 the a/d in power-down and idle modes . . . . 15 8.4.2 code examples for the a/d. . . . . . . . . . . . . . . 16 8.5 digital to analog converter (dac) outputs . . . 17 8.6 analog comparators . . . . . . . . . . . . . . . . . . . . 17 8.6.1 comparator con?guration . . . . . . . . . . . . . . . . 18 8.6.2 internal reference voltage . . . . . . . . . . . . . . . . 19 8.6.3 comparator interrupt. . . . . . . . . . . . . . . . . . . . 20 8.6.4 comparators and power reduction modes . . . 20 8.6.5 comparator con?guration example. . . . . . . . . 20 8.7 i 2 c-bus serial interface . . . . . . . . . . . . . . . . . . 20 8.7.1 i 2 c-bus interrupts . . . . . . . . . . . . . . . . . . . . . . 22 8.7.2 reading i2con . . . . . . . . . . . . . . . . . . . . . . . 23 8.7.3 checking atn and drdy . . . . . . . . . . . . . . . . 23 8.7.4 writing i2con . . . . . . . . . . . . . . . . . . . . . . . . 24 8.7.5 regarding transmit active . . . . . . . . . . . . . . . 24 8.7.6 regarding software response time . . . . . . . . . 25 8.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.8.1 external interrupt inputs . . . . . . . . . . . . . . . . . 28 8.9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.9.1 quasi-bidirectional output con?guration . . . . . 29 8.9.2 open drain output con?guration . . . . . . . . . . . 30 8.9.3 push-pull output con?guration . . . . . . . . . . . . 31 8.9.4 keyboard interrupt (kbi) . . . . . . . . . . . . . . . . . 33 8.10 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.10.1 low speed oscillator option . . . . . . . . . . . . . . 34 8.10.2 medium speed oscillator option . . . . . . . . . . . 34 8.10.3 high speed oscillator option. . . . . . . . . . . . . . 34 8.10.4 on-chip rc oscillator option . . . . . . . . . . . . . . 35 8.10.5 external clock input option . . . . . . . . . . . . . . . 35 8.10.6 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.10.7 cpu clock modi?cation: clkr and divm . . . 36 8.11 power monitoring functions. . . . . . . . . . . . . . . 37 8.11.1 brownout detection . . . . . . . . . . . . . . . . . . . . . 37 8.11.2 power-on detection . . . . . . . . . . . . . . . . . . . . . 38 8.12 power reduction modes . . . . . . . . . . . . . . . . . 38 8.12.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.12.2 power-down mode . . . . . . . . . . . . . . . . . . . . . 38 8.12.3 low voltage eprom operation . . . . . . . . . . . 39 8.13 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.14 timer/counters . . . . . . . . . . . . . . . . . . . . . . . . 41 8.14.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.14.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.14.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.14.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.14.5 timer over?ow toggle output . . . . . . . . . . . . . 45 8.15 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.15.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.15.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.15.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.15.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.15.5 serial port control register (scon) . . . . . . . . 46 8.15.6 baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.15.7 using timer1 to generate baud rates. . . . . . . 48 8.15.8 more about uart mode 0 . . . . . . . . . . . . . . . 49 8.15.9 more about uart mode 1 . . . . . . . . . . . . . . . 50 8.15.10 more about uart modes 2 and 3 . . . . . . . . . 51 8.15.11 multiprocessor communications . . . . . . . . . . . 52 8.15.12 automatic address recognition . . . . . . . . . . . . 52 8.16 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 58 8.16.1 watchdog feed sequence. . . . . . . . . . . . . . . . 59 8.16.2 watchdog reset . . . . . . . . . . . . . . . . . . . . . . . 59 8.17 additional features . . . . . . . . . . . . . . . . . . . . . 60 8.17.1 software reset . . . . . . . . . . . . . . . . . . . . . . . . 61 8.17.2 dual data pointers . . . . . . . . . . . . . . . . . . . . . 61 8.18 eprom characteristics . . . . . . . . . . . . . . . . . 61 8.18.1 system con?guration bytes . . . . . . . . . . . . . . 62 8.18.2 security bits . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 64 10 static characteristics . . . . . . . . . . . . . . . . . . . 65 11 dynamic characteristics . . . . . . . . . . . . . . . . . 69 12 comparator electrical characteristics . . . . . . 70 13 d/a electrical characteristics . . . . . . . . . . . . . 70 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 71 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 72 16 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 73 17 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 18 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 19 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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